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this is information on a product in full production. october 2013 docid023953 rev 4 1/126 spc56el70l3, spc56el70l5 spc564l70l3, spc564l70l5 32-bit power architecture ? microcontroller for automotive sil3/asild chassis and safety applications datasheet - production data features ? high-performance e200z4d dual core ? 32-bit power architecture ? technology cpu ? core frequency as high as 120 mhz ? dual issue five-stage pipeline core ? variable length encoding (vle) ? memory management unit (mmu) ? 4 kb instruction cache with error detection code ? signal processing engine (spe) ? memory available ? 2 mb flash memory with ecc ? 192 kb on-chip sram with ecc ? built-in rww capabilities for eeprom emulation ? sil3/asild innovative safety concept: lock step mode and fail-safe protection ? sphere of replication (sor) for key components (such as cpu core, edma, crossbar switch) ? fault collection and control unit (fccu) ? redundancy control and checker unit (rccu) on outputs of the sor connected to fccu ? boot-time built-in self-test for memory (mbist) and logic (lbist) triggered by hardware ? boot-time built-in self-test for adc and flash memory triggered by software ? replicated safety enhanced watchdog ? replicated junction temperature sensor ? non maskable interrupt (nmi) ? 16-region memory protection unit (mpu) ? clock monitoring units (cmu) ? power management unit (pmu) ? cyclic redundancy check (crc) unit ? decoupled parallel mode for high performance use of replicated cores ? nexus class 3+ interface ? interrupts ? replicated 16-priority controller ? replicated 16-channel edma controller ? gpios individually programmable as input, output or special function ? three 6-channel general-purpose etimer units ? 2 flexpwm units: four 16-bit channels per module ? communications interfaces ? 2 linflexd channels ? 3 dspi channels with automatic chip select generation ? 3 flexcan interfaces (2.0b active) with 32 message objects ? flexray module (v2.1 rev. a) with 2 channels, 64 message buffers and data rates up to 10 mbit/s ? two 12-bit analog-to-digital converters (adc) ? 16 input channels ? programmable cross triggering unit (ctu) to synchronize adcs conversion with timer and pwm ? sine wave generator (d/a with low pass filter) ? on-chip can/uart/flexray bootstrap loader ? single 3.0 v to 3.6 v voltage supply ? ambient temperature range ?40 c to 125 c ? junction temperature range ?40 c to 150 c lqfp100 (14 x 14x 1.4 mm) lqfp144 (20 x 20 x 1.4 mm) www.st.com
contents spc56xl70lx 2/126 docid023953 rev 4 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 1.5 feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5.1 high-performance e200z4d core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5.2 crossbar switch (xbar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.3 memory protection unit (mpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.4 enhanced direct memory access (edma) . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.5 on-chip flash memory with ecc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5.6 on-chip sram with ecc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5.7 platform flash memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5.8 platform static ram controller (sramc) . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5.9 memory subsystem access time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5.10 error correction status module (ecsm) . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5.11 peripheral bridge (pbridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.12 interrupt controller (intc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.13 system clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5.14 frequency-modulated phase-locked loop (fmpll) . . . . . . . . . . . . . . 18 1.5.15 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.16 internal reference clock (rc) oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.17 clock, reset, power, mode and test control modules (mc_cgm, mc_rgm, mc_pcu, and mc_me) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.18 periodic interrupt timer module (pit) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.19 system timer module (stm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5.20 software watchdog timer (swt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5.21 fault collection and control unit (fccu) . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5.22 system integration unit lite (siul) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5.23 non-maskable interrupt (nmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.5.24 boot assist module (bam) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.5.25 system status and configuration module (sscm) . . . . . . . . . . . . . . . . . 21 1.5.26 flexcan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.5.27 flexray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
docid023953 rev 4 3/126 spc56xl70lx contents 4 1.5.28 serial communication interface module (linflexd) . . . . . . . . . . . . . . . 24 1.5.29 deserial serial peripheral interface (dspi) . . . . . . . . . . . . . . . . . . . . . . 25 1.5.30 flexpwm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.5.31 etimer module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.32 sine wave generator (swg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.33 analog-to-digital converter module (adc) . . . . . . . . . . . . . . . . . . . . . . 28 1.5.34 cross triggering unit (ctu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.5.35 cyclic redundancy checker ( crc) unit . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.36 redundancy control and checker unit (rccu) . . . . . . . . . . . . . . . . . . . 29 1.5.37 junction temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5.38 nexus port controller (npc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5.39 ieee 1149.1 jtag controller (jtagc) . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.5.40 voltage regulator / power management unit (pmu) . . . . . . . . . . . . . . . . 31 1.5.41 built-in self-test (bist) capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2 package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 33 2.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2 supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.3 system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.4 pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.4.1 general notes for specifications at maximum junction temperature . . . 77 3.5 electromagnetic interference (emi) characteristics . . . . . . . . . . . . . . . . . 79 3.6 electrostatic discharge (esd) characteristics . . . . . . . . . . . . . . . . . . . . . 80 3.7 static latch-up (lu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.8 voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 81 3.9 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.10 temperature sensor electrical characteristics . . . . . . . . . . . . . . . . . . . . . 87 3.11 main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.12 fmpll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
contents spc56xl70lx 4/126 docid023953 rev 4 3.13 16 mhz rc oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . 91 3.14 adc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.14.1 input impedance and adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.15 flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.16 swg electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.17 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.17.1 pad ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.18 reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3.18.1 reset sequence duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3.18.2 reset sequence description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.18.3 reset sequence trigger mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 3.18.4 reset sequence ? start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.18.5 external watchdog window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 3.19 ac timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 3.19.1 reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 3.19.2 wkup/nmi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 3.19.3 ieee 1149.1 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 3.19.4 nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 3.19.5 external interrupt timing (irq pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 3.19.6 dspi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.1 ecopack? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 4.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
docid023953 rev 4 5/126 spc56xl70lx list of tables 5 list of tables table 1. spc56xl70/spc56x64 device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. platform memory access time summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 3. lqfp100 pin function summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 table 4. lqfp144 pin function summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 table 5. supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 6. system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 7. pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 9. recommended operating conditions (3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 10. thermal characteristics for lqfp100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 11. thermal characteristics for lqfp144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 12. emi configuration summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 13. emi emission testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 14. esd ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 15. latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 16. recommended operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 17. voltage regulator electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 18. dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 19. current consumption characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 20. temperature sensor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 21. main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 22. fmpll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 23. rc oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 24. adc conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 25. flash memory program and erase electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 96 table 26. flash memory timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 27. flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 28. spc56xl70 swg specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 29. pad ac specifications (3.3 v , ipp_hve = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 30. reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 31. reset sequence trigger ? reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 32. voltage thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 33. reset electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 34. wkup/nmi glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 35. jtag pin ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 07 table 36. nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 37. external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 38. dspi timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 39. lqfp100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 40. lqfp144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 41. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
list of figures spc56xl70lx 6/126 docid023953 rev 4 list of figures figure 1. spc56el70 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. spc56xl70 lqfp100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 3. spc56xl70 lqfp144 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 4. bcp68 board schematic example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 5. crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 6. main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 7. adc characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1 figure 8. input equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 9. transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 10. spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 11. pad output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 12. destructive reset sequence, bist enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 13. destructive reset sequence, bist disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 14. external reset sequence long, bist enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 15. functional reset sequence long. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 01 figure 16. functional reset sequence short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 02 figure 17. reset sequence start for destructive resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 18. reset sequence start via reset assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 19. reset sequence - external watchdog trigger window position . . . . . . . . . . . . . . . . . . . . . 105 figure 20. start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 21. noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 22. jtag test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 23. jtag test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 24. jtag boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 25. nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 26. nexus ddr mode output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 10 figure 27. nexus tdi, tms, tdo timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 28. external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 29. dspi classic spi timing ? master, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 30. dspi classic spi timing ? master, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 31. dspi classic spi timing ? slave, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 32. dspi classic spi timing ? slave, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 33. dspi modified transfer format timing ? master, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . 116 figure 34. dspi modified transfer format timing ? master, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . 116 figure 35. dspi modified transfer format timing ? slave, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 36. dspi modified transfer format timing ? slave, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 37. dspi pcs strobe (pcss) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 18 figure 38. lqfp100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 39. lqfp144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 40. commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 23
docid023953 rev 4 7/126 spc56xl70lx introduction 125 1 introduction 1.1 document overview this document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the devices. this document provides electrical specifications, pin assignments, and package diagrams for the spc56xl70 series of microcontroller units (mcus). for functional characteristics, see the spc56xl70 microcontroller reference manual. for use of the spc56xl70 in a fail- safe system according to safety standard iso26262, see the safety application guide for spcel70. 1.2 description the spc56xl70 series microcontrollers are system-on-chip devices that are built on power architecture technology and contain enhancements that improve the architecture?s fit in embedded applications, include additional instruction support for digital signal processing (dsp) and integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital converter, controller area network, and an enhanced modular input-output system. the spc56xl70 family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. it belongs to an expanding range of automotive-focused products designed to address electrical hydraulic power steering (ehps), electric power steering (eps) and airbag applications. the advanced and cost-efficient host processor core of the spc56xl70 automotive controller family complies with the power architecture embedded category. it operates at speeds as high as 120 mhz and offers high-performance processing optimized for low power consumption. it capitalizes on the available development infrastructure of current power architecture devices and is supported with software drivers, operating systems and configuration code to assist with users? implementations.
introduction spc56xl70lx 8/126 docid023953 rev 4 1.3 device comparison table 1. spc56xl70/spc56x64 device summary feature spc56el64 spc56el70 spc564l64 spc564l70 cpu type 2 e200z4 (in lock-step or decoupled operation) 2 e200z4 (in lock-step or decoupled operation) 1 e200z4 1 e200z4 architecture harvard execution speed 0?120 mhz (+2% fm) dmips intrinsic performance >240 mips simd (dsp + fpu) yes mmu 16 entry instruction set ppc yes instruction set vle yes instruction cache 4 kb, edc mpu-16 regions yes, replicated module semaphore unit (sema4) yes buses core bus ahb, 32-bit address, 64-bit data internal periphery bus 32-bit address, 32-bit data crossbar master slave ports lock step mode: 4 3 decoupled parallel mode: 6 3 4x3 memory code/data flash 1.5 mb, ecc, rww 2 mb, ecc, rww 1.5 mb, ecc, rww 2 mb, ecc, rww static ram (sram) 160 kb, ecc 192 kb, ecc 160 kb, ecc 192 kb, ecc
docid023953 rev 4 9/126 spc56xl70lx introduction 125 modules interrupt controller (intc) 16 interrupt levels, replicated module periodic interrupt timer (pit) 1 4 channels system timer module (stm) 1 4 channels, replicated module software watchdog timer (swt) yes, replicated module edma 16 channels, replicated module flexray 1 64 message buffers, dual channel flexcan 3 32 message buffers linflexd (uart and lin with dma support) 2 clock out yes fault collection and control unit (fccu) yes cross triggering unit (ctu) yes etimer 3 6 channels (1) flexpwm 2 module 4 (2 + 1) channels (2) analog-to- digital converter (adc) 2 12-bit adc, 16 channels per adc (3 internal, 4 shared and 9 external) sine wave generator (swg) 32 point table 1. spc56xl70/spc56x64 device summary (continued) feature spc56el64 spc56el70 spc564l64 spc564l70
introduction spc56xl70lx 10/126 docid023953 rev 4 modules (cont.) deserial serial peripheral interface (dspi) 3 dspi as many as 8 chip selects cyclic redundancy checker (crc) unit yes junction temperature sensor (tsens) yes, replicated module digital i/os 16 supply device power supply 3.3 v with integrated bypassable ballast transistor external ballast transistor not needed for bare die analog reference voltage 3.0 v ? 3.6 v and 4.5 v ? 5.5 v clocking frequency- modulated phase-locked loop (fmpll) 2 internal rc oscillator 16 mhz external crystal oscillator 4?40mhz debug nexus level 3+ package s lqfp 100 pins 144 pins temperat ure temperature range (junction) ?40 to 150 c ambient temperature range using external ballast transistor (lqfp) ?40 to 125 c 1. the third etimer is not connected to any pins on the package. its usage is confined internally to the device. 2. the second flexpwm is not connected to any pins on the package. its usage is confined internally to the device. table 1. spc56xl70/spc56x64 device summary (continued) feature spc56el64 spc56el70 spc564l64 spc564l70
docid023953 rev 4 11/126 spc56xl70lx introduction 125 1.4 block diagram figure 1 shows a top-level block diagram of the spc56el70 device. figure 1. spc56el70 block diagram adc ? analog-to-digital converter bam ? boot assist module cmu ? clock monitoring unit crc ? cyclic redundancy check unit ctu ? cross triggering unit dspi ? serial peripherals interface ecc ? error correction code ecsm ? error correction status module edma ? enhanced direct memory access controller fccu ? fault collection and control unit flexcan ? controller area network controller fmpll ? frequency modulated phase locked loop intc ? interrupt controller ircosc ? internal rc oscillator jtag ? joint test action group interface linflexd ? lin controller with dma support mc ? mode entry, clock, reset, & power pbridge ? peripheral bridge pit ? periodic interrupt timer pmu ? power management unit rc ? redundancy checker rtc ? real time clock sema4 ? semaphore unit siul ? system integration unit lite sscm ? system status and configuration module stm ? system timer module swg ? sine wave generator swt ? software watchdog timer tsens ? temperature sensor xosc ? crystal oscillator sram pmu swt ecsm stm intc edma crossbar switch vle mmu i-cache spe e200z4 vle mmu i-cache spe e200z4 memory protection unit crossbar switch memory protection unit pbridge jtag nexus jtag nexus rc rc rc rc flexray pbridge tsens tsens ecc bits flash memory ecc bits + logic siul mc wakeup adc adc xosc bam sscm secondary fmpll fmpll ircosc cmu cmu ctu pit fccu flexpwm flexpwm etimer etimer etimer flexcan flexcan linflexd linflexd dspi dspi dspi crc cmu sema4 swt ecsm stm intc edma sema4 swg ecc logic for sram ecc logic for sram flexcan
introduction spc56xl70lx 12/126 docid023953 rev 4 1.5 feature details 1.5.1 high-performance e200z4d core the e200z4d power architecture ? core provides the following features: ? 2 independent execution units, both supporting fixed-point and floating-point operations ? dual issue 32-bit power architecture technology compliant ? 5-stage pipeline (if, dec, ex1, ex2, wb) ? in-order execution and instruction retirement ? full support for power architecture instruction set and variable length encoding (vle) ? mix of classic 32-bit and 16-bit instruction allowed ? optimization of code size possible ? thirty-two 64-bit general purpose registers (gprs) ? harvard bus (32-bit address, 64-bit data) ? i-bus interface capable of one outstanding transaction plus one piped with no wait- on-data return ? d-bus interface capable of two transactions outstanding to fill ahb pipe ? i-cache and i-cache controller ? 4 kb, 256-bit cache line (programmable for 2- or 4-way) ? no data cache ? 16-entry mmu ? 8-entry branch table buffer ? branch look-ahead instruction buffer to accelerate branching ? dedicated branch address calculator ? 3 cycles worst case for missed branch ? load/store unit ? fully pipelined ? single-cycle load latency ? big- and little-endian modes supported ? misaligned access support ? single stall cycle on load to use ? single-cycle throughput (2-cycle latency) integer 32 32 multiplication ? 4 ? 14 cycles integer 32 32 division (average division on various benchmark of nine cycles) ? single precision floating-point unit ? 1 cycle throughput (2-cycle latency) floating-point 32 32 multiplication ? target 9 cycles (worst case acceptable is 12 cycles) throughput floating-point 32 32 division ? special square root and min/max function implemented ? signal processing support: apu-spe 1.1 ? support for vectorized mode: as many as two floating-point instructions per clock ? vectored interrupt support ? reservation instruction to support read-modify-write constructs
docid023953 rev 4 13/126 spc56xl70lx introduction 125 ? extensive system development and tracing support via nexus debug port 1.5.2 crossbar switch (xbar) the xbar multi-port crossbar switch supports simultaneous connections between four master ports and three slave ports. the crossbar supports a 32-bit address bus width and a 64-bit data bus width. the crossbar allows four concurrent transactions to occur from any master port to any slave port, although one of those transfers must be an instruction fetch from internal flash memory. if a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. all other masters requesting that slave port are stalled until the higher priority master completes its transactions. the crossbar provides the following features: ? 4 masters and 3 slaves supported per each replicated crossbar ? masters allocation for each crossbar: e200z4d core with two independent bus interface units (biu) for i and d access (2 masters), one edma, one flexray ? slaves allocation for each crossbar: a redundant flash-memory controller with 2 slave ports to guarantee maximum flexibility to handle instruction and data array, one redundant sram controller with 1 slave port each and 1 redundant peripheral bus bridge ? 32-bit address bus and 64-bit data bus ? programmable arbitration priority ? requesting masters can be treated with equal priority and are granted access to a slave port in round-robin method, based upon the id of the last master to be granted access or a priority order can be assigned by software at application run time ? temporary dynamic priority elevation of masters the xbar is replicated for each processing channel. 1.5.3 memory protection unit (mpu) the memory protection unit splits the physical memory into 16 different regions. each master (edma, flexray, cpu) can be assigned different access rights to each region. ? 16-region mpu with concurrent checks against each master access ? 32-byte granularity for protected address region the memory protection unit is replicated for each processing channel. 1.5.4 enhanced direct memory access (edma) the enhanced direct memory access (edma) controller is a second-generation module capable of performing complex data movements via 16 programmable channels, with minimal intervention from the host processor. the hardware microarchitecture includes a dma engine which performs source and destination address calculations, and the actual data movement operations, along with an sram-based memory containing the transfer control descriptors (tcd) for the channels. this implementation is used to minimize the overall block size.
introduction spc56xl70lx 14/126 docid023953 rev 4 the edma module provides the following features: ? 16 channels supporting 8-, 16-, and 32-bit value single or block transfers ? support variable sized queues and circular buffered queue ? source and destination address registers independently configured to post-increment or stay constant ? support major and minor loop offset ? support minor and major loop done signals ? dma task initiated either by hardware requestor or by software ? each dma task can optionally generate an interrupt at completion and retirement of the task ? signal to indicate closure of last minor loop ? transfer control descriptors mapped inside the sram the edma controller is replicated for each processing channel. 1.5.5 on-chip flash memory with ecc this device includes programmable, non-volatile flash memory. the non-volatile memory (nvm) can be used for instruction storage or data storage, or both. the flash memory module interfaces with the system bus through a dedicated flash memory array controller. it supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory. the module contains four 128-bit prefetch buffers. prefetch buffer hits allow no-wait responses. buffer misses incur a 3 wait state response at 120 mhz. the flash memory module provides the following features: ? 2 mb of flash memory in unique multi-partitioned hard macro ? sectorization: ? partition 1 (low address): 16 kb + 16 kb + 16 kb + 16 kb ? partition 2 (low address): 16 kb + 16 kb + 16 kb + 16 kb ? partition 3 (low address): 64 kb + 64 kb ? partition 4 (mid address): 128 kb + 128 kb ? partition 5 (high address): 256 kb + 256 kb ? partition 6 (high address): 256 kb + 256 kb ? partition 7 (high address): 256 kb + 256 kb ? eeprom emulation (in software) within same module but on different partition ? 16 kb test sector and 16 kb shadow sector for test, censorship device and user option bits ? wait states: ? access time less or equal to 3 ws at 120 mhz + 4% fm (4-1-2-1 access) ? access time less or equal to 2 ws at 80 mhz + 4% fm ? flash memory line 128-bit wide with 8-bit ecc on 64-bit word (total 144 bits) ? accessed via a 64-bit wide bus for write and a 128-bit wide array for read operations ? 1-bit error correction, 2-bit error detection 1.5.6 on-chip sram with ecc the spc56xl70 sram provides a general-purpose single port memory.
docid023953 rev 4 15/126 spc56xl70lx introduction 125 ecc handling is done on a 32-bit boundary for data and it is extended to the address to have the highest possible diagnostic coverage including the array internal address decoder. the sram module provides the following features: ? system sram: 192 kb ? ecc on 32-bit word (syndrome of 7 bits) ? ecc covers sram bus address ? 1-bit error correction, 2-bit error detection ? wait states: ? 1 wait state at 120 mhz ? 0 wait states at 80 mhz 1.5.7 platform flash memory controller the following list summarizes the key features of the flash memory controller: ? single ahb port interface supports a 64-bit data bus. all ahb aligned and unaligned reads within the 32-bit container are supported. only aligned word writes are supported. ? array interfaces support a 128-bit read data bus and a 64-bit write data bus for each bank. ? code flash (bank0) interface provides configurable read buffering and page prefetch support. ? four page-read buffers (each 128 bits wide) and a prefetch controller support speculative reading and optimized flash access. ? single-cycle read responses (0 ahb data-phase wait states) for hits in the buffers. the buffers implement a least-recently-used replacement algorithm to maximize performance. ? data flash (bank1) interface includes a 128-bit register to temporarily hold a single flash page. this logic supports single-cycle read responses (0 ahb data-phase wait states) for accesses that hit in the holding register. ? no prefetch support is provided for this bank. ? programmable response for read-while-write sequences including support for stall- while-write, optional stall notification interrupt, optional flash operation abort , and optional abort notification interrupt. ? separate and independent configurable access timing (on a per bank basis) to support use across a wide range of platforms and frequencies. ? support of address-based read access timing for emulation of other memory types. ? support for reporting of single- and multi-bit error events. ? typical operating configuration loaded into programming model by system reset. the platform flash controller is replicated for each processor. 1.5.8 platform static ram controller (sramc) the sramc module is the platform sram array controller, with integrated error detection and correction.
introduction spc56xl70lx 16/126 docid023953 rev 4 the main features of the sramc provide connectivity for the following interfaces: ? xbar slave port (64-bit data path) ? ecsm (ecc error reporting, error injection and configuration) ? sram array the following functions are implemented: ? ecc encoding (32-bit boundary for data and complete address bus) ? ecc decoding (32-bit boundary and entire address) ? address translation from the ahb protocol on the xbar to the sram array the platform sram controller is replicated for each processor. 1.5.9 memory subsystem access time every memory access the cpu performs requires at least one system clock cycle for the data phase of the access. slower memories or peripherals may require additional data phase wait states. additional data phase wait states may also occur if the slave being accessed is not parked on the requesting master in the crossbar. ta ble 2 shows the number of additional data phase wait states required for a range of memory accesses. 1.5.10 error correction status module (ecsm) the ecsm on this device manages the ecc configuration and reporting for the platform memories (flash memory and sram). it does not implement the actual ecc calculation. a detected error (double error for flash memory or sram) is also reported to the fccu. the following errors and indications are reported into the ecsm dedicated registers: ? ecc error status and configuration for flash memory and sram ? ecc error reporting for flash memory ? ecc error reporting for sram ? ecc error injection for sram table 2. platform memory access time summary ahb transfer data phase wait states description e200z4d instruction fetch 0 flash memory prefetch buffer hit (page hit) e200z4d instruction fetch 3 flash memory prefetch buffer miss (based on 4-cycle random flash array access time) e200z4d data read 0?1 sram read e200z4d data write 0 sram 32-bit write e200z4d data write 0 sram 64-bit write (executed as 2 x 32-bit writes) e200z4d data write 0?2 sram 8-,16-bit write (read-modify-write for ecc) e200z4d flash memory read 0 flash memory prefetch buffer hit (page hit) e200z4d flash memory read 3 flash memory prefetch buffer miss (at 120 mhz; includes 1 cycle of program flash memory controller arbitration)
docid023953 rev 4 17/126 spc56xl70lx introduction 125 1.5.11 peripheral bridge (pbridge) the pbridge implements the following features: ? duplicated periphery ? master access right per peripheral (per master: read access enable; write access enable) ? checker applied on pbridge output toward periphery ? byte endianess swap capability 1.5.12 interrupt controller (intc) the intc provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. for high-priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (isr) has been minimized. the intc provides a unique vector for each interrupt request source for quick determination of which isr needs to be executed. it also provides an ample number of priorities so that lower priority isrs do not delay the execution of higher priority isrs. to allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. the intc supports the priority ceiling protocol for coherent accesses. by providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. the intc provides the following features: ? duplicated periphery ? unique 9-bit vector per interrupt source ? 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source ? priority elevation for shared resource the intc is replicated for each processor.
introduction spc56xl70lx 18/126 docid023953 rev 4 1.5.13 system clocks and clock generation the following list summarizes the system clock and clock generation on this device: ? lock status continuously monitored by lock detect circuitry ? loss-of-clock (loc) detection for reference and feedback clocks ? on-chip loop filter (for improved electromagnetic interference performance and fewer external components required) ? programmable output clock divider of system clock ( 1, 2, 4, 8) ? flexpwm module and as many as three etimer modules running on an auxiliary clock independent from system clock (with max frequency 120 mhz) ? on-chip crystal oscillator with automatic level control ? dedicated internal 16 mhz internal rc oscillator for rapid start-up ? supports automated frequency trimming by hardware during device startup and by user application ? auxiliary clock domain for motor control periphery (flexpwm, etimer, ctu, adc, and swg) 1.5.14 frequency-modulated phase-locked loop (fmpll) each device has two fmplls. each fmpll allows the user to generate high speed system clocks starting from a minimum reference of 4 mhz input clock. further, the fmpll supports programmable frequency modulation of the system clock. the fmpll multiplication factor, output clock divider ratio are all software configurable. the fmplls have the following major features: ? input frequency: 4?40 mhz continuous range (limited by the crystal oscillator) ? voltage controlled oscillator (vco) range: 256?512 mhz ? frequency modulation via software control to reduce and control emission peaks ? modulation depth 2% if centered or 0% to ?4% if downshifted via software control register ? modulation frequency: triangular modulation with 25 khz nominal rate ? option to switch modulation on and off via software interface ? reduced frequency divider (rfd) for reduced frequency operation without re-lock ? 3 modes of operation ? bypass mode ? normal fmpll mode with crystal reference (default) ? normal fmpll mode with external reference ? lock monitor circuitry with lock status ? loss-of-lock detection for reference and feedback clocks ? self-clocked mode (scm) operation ? on-chip loop filter ? auxiliary fmpll ? used for flexray due to precise symbol rate requirement by the protocol ? used for motor control periphery and connected ip (a/d digital interface ctu) to allow independent frequencies of operation for pwm and timers and jitter-free control
docid023953 rev 4 19/126 spc56xl70lx introduction 125 ? option to enable/disable modulation to avoid protocol violation on jitter and/or potential unadjusted error in electric motor control loop ? allows to run motor control periphery at different (precisely lower, equal or higher as required) frequency than the system to ensure higher resolution 1.5.15 main oscillator the main oscillator provides these features: ? input frequency range 4?40 mhz ? crystal input mode ? external reference clock (3.3 v) input mode ? fmpll reference 1.5.16 internal reference clock (rc) oscillator the architecture uses constant current charging of a capacitor. the voltage at the capacitor is compared to the stable bandgap reference voltage. the rc oscillator is the device safe clock. the rc oscillator provides these features: ? nominal frequency 16 mhz ? 5% variation over voltage and temperature after process trim ? clock output of the rc oscillator serves as system clock source in case loss of lock or loss of clock is detected by the fmpll ? rc oscillator is used as the default system clock during startup and can be used as back-up input source of fmpll(s) in case xosc fails 1.5.17 clock, reset, power, mode and test control modules (mc_cgm, mc_rgm, mc_pcu, and mc_me) these modules provide the following: ? clock gating and clock distribution control ? halt, stop mode control ? flexible configurable system and auxiliary clock dividers ? various execution modes ? halt and stop mode as reduced activity low power mode ? reset, idle, test, safe ? various run modes with software selectable powered modules ? no stand-by mode implemented (no internal switchable power domains) 1.5.18 periodic interrupt timer module (pit) the pit module implements the following features: ? 4 general purpose interrupt timers ? 32-bit counter resolution ? can be used for software tick or dma trigger operation
introduction spc56xl70lx 20/126 docid023953 rev 4 1.5.19 system timer module (stm) the stm implements the following features: ? up-counter with 4 output compare registers ? os task protection and hardware tick implementation per autosar (a) requirement the stm is replicated for each processor. 1.5.20 software watchdog timer (swt) this module implements the following features: ? fault tolerant output ? safe internal rc oscillator as reference clock ? windowed watchdog ? program flow control monitor with 16-bit pseudorandom key generation ? allows a high level of safety (sil3 monitor) the swt module is replicated for each processor. 1.5.21 fault collection and control unit (fccu) the fccu module has th e following features: ? redundant collection of hardware checker results ? redundant collection of error information and latch of faults from critical modules on the device ? collection of self-test results ? configurable and graded fault control ? internal reactions (no internal reaction, irq, functional reset, destructive reset, or safe mode entered) ? external reaction (failure is reported to the external/surrounding system via configurable output pins) 1.5.22 system integration unit lite (siul) the siul controls mcu reset configuration, pad configuration, external interrupt, general purpose i/o (gpio), internal peripheral multiplexing, and system reset operation. the reset configuration block contains the external pin boot configuration logic. the pad configuration block controls the static electrical characteristics of i/o pins. the gpio block provides uniform and discrete input/output control of the i/o pins of the mcu. a. automotive open system architecture
docid023953 rev 4 21/126 spc56xl70lx introduction 125 the siu provides the following features: ? centralized pad control on a per-pin basis ? pin function selection ? configurable weak pull-up/down ? configurable slew rate control (slow/medium/fast) ? hysteresis on gpio pins ? configurable automatic safe mode pad control ? input filtering for external interrupts 1.5.23 non-maskable interrupt (nmi) the non-maskable interrupt with de-glitching filter supports high-priority core exceptions. 1.5.24 boot assist module (bam) the bam is a block of read-only memory with hard-coded content. the bam program is executed only if serial booting mode is selected via boot configuration pins. the bam provides the following features: ? enables booting via serial mode (flexcan or linflex-uart) ? supports programmable 64-bit password protection for serial boot mode ? supports serial bootloading of either power architecture code (default) or vle code ? automatic switch to serial boot mode if internal flash memory is blank or invalid 1.5.25 system status and configuration module (sscm) the sscm on this device features the following: ? system configuration and status ? debug port status and debug port enable ? multiple boot code starting locations out of reset through implementation of search for valid reset configuration half word ? sets up the mmu to allow user boot code to execute as either power architecture code (default) or as vle code out of flash memory ? triggering of device self-tests during reset phase of device boot 1.5.26 flexcan the flexcan module is a communication controller implementing the can protocol according to bosch specification version 2.0b. the can protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real- time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness and required bandwidth.
introduction spc56xl70lx 22/126 docid023953 rev 4 the flexcan module provides the following features: ? full implementation of the can protocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? 0 to 8 bytes data length ? programmable bit rate as fast as 1mbit/s ? 32 message buffers of 0 to 8 bytes data length ? each message buffer configurable as receive or transmit buffer, all supporting standard and extended messages ? programmable loop-back mode supporting self-test operation ? 3 programmable mask registers ? programmable transmit-first scheme: lowest id or lowest buffer number ? time stamp based on 16-bit free-running timer ? global network time, synchronized by a specific message ? maskable interrupts ? independent of the transmission medium (an external transceiver is assumed) ? high immunity to emi ? short latency time due to an arbitration scheme for high-priority messages ? transmit features ? supports configuration of multiple mailboxes to form message queues of scalable depth ? arbitration scheme according to message id or message buffer number ? internal arbitration to guarantee no inner or outer priority inversion ? transmit abort procedure and notification ? receive features ? individual programmable filters for each mailbox ? 8 mailboxes configurable as a 6-entry receive fifo ? 8 programmable acceptance filters for receive fifo ? programmable clock source ? system clock ? direct oscillator clock to avoid fmpll jitter
docid023953 rev 4 23/126 spc56xl70lx introduction 125 1.5.27 flexray the flexray module provides the following features: ? full implementation of flexray protocol specification 2.1 rev. a ? 64 configurable message buffers can be handled ? dual channel or single channel mode of operation, each as fast as 10 mbit/s data rate ? message buffers configurable as transmit or receive ? message buffer size configurable ? message filtering for all message buffers based on frame id, cycle count, and message id ? programmable acceptance filters for receive fifo ? message buffer header, status, and payload data stored in system memory (sram) ? internal flexray memories have error detection and correction
introduction spc56xl70lx 24/126 docid023953 rev 4 1.5.28 serial communication interface module (linflexd) the linflexd module (linflex with dma support) on this device features the following: ? supports lin master mode, lin slave mode and uart mode ? lin state machine compliant to lin1.3, 2.0, and 2.1 specifications ? manages lin frame transmission and reception without cpu intervention ? lin features ? autonomous lin frame handling ? message buffer to store as many as 8 data bytes ? supports messages as long as 64 bytes ? detection and flagging of lin errors (sync field, delimiter, id parity, bit framing, checksum and time-out errors) ? classic or extended checksum calculation ? configurable break duration of up to 50-bit times ? programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) ? diagnostic features (loop back, lin bus stuck dominant detection) ? interrupt driven operation with 16 interrupt sources ? lin slave mode features ? autonomous lin header handling ? autonomous lin response handling ? uart mode ? full-duplex operation ? standard non return-to-zero (nrz) mark/space format ? data buffers with 4-byte receive, 4-byte transmit ? configurable word length (8-bit, 9-bit, or 16-bit words) ? configurable parity scheme: none, odd, even, always 0 ? speed as fast as 2 mbit/s ? error detection and flagging (parity, noise and framing errors) ? interrupt driven operation with four interrupt sources ? separate transmitter and receiver cpu interrupt sources ? 16-bit programmable baud-rate modulus counter and 16-bit fractional ? 2 receiver wake-up methods ? support for dma enabled transfers
docid023953 rev 4 25/126 spc56xl70lx introduction 125 1.5.29 deserial serial peripheral interface (dspi) the dspi modules provide a synchronous serial interface for communication between the spc56xl70 and external devices. a dspi module provides these features: ? full duplex, synchronous transfers ? master or slave operation ? programmable master bit rates ? programmable clock polarity and phase ? end-of-transmission interrupt flag ? programmable transfer baud rate ? programmable data frames from 4 to 16 bits ? as many as 8 chip select lines available, depending on package and pin multiplexing ? 4 clock and transfer attributes registers ? chip select strobe available as alternate function on one of the chip select pins for de- glitching ? fifos for buffering as many as 5 transfers on the transmit and receive side ? queueing operation possible through use of the edma ? general purpose i/o functionality on pins when not used for spi 1.5.30 flexpwm the pulse width modulator module (flexpwm) contains four pwm channels, each of which is configured to control a single half-bridge power stage. one module is present in lqfp144 package. additionally, four fault input channels are provided per flexpwm module. this pwm is capable of controlling most motor types, including: ? ac induction motors (acim) ? permanent magnet ac motors (pmac) ? brushless (bldc) and brush dc motors (bdc) ? switched (srm) and variable reluctance motors (vrm) ? stepper motors
introduction spc56xl70lx 26/126 docid023953 rev 4 a flexpwm module implements the following features: ? 16 bits of resolution for center, edge aligned, and asymmetrical pwms ? maximum operating frequency as high as 120 mhz ? clock source not modulated and independent from system clock (generated via secondary fmpll) ? fine granularity control for enhanced resolution of the pwm period ? pwm outputs can operate as complementary pairs or independent channels ? ability to accept signed numbers for pwm generation ? independent control of both edges of each pwm output ? synchronization to external hardware or other pwm supported ? double buffered pwm registers ? integral reload rates from 1 to 16 ? half cycle reload capability ? multiple adc trigger events can be generated per pwm cycle via hardware ? fault inputs can be assigned to control multiple pwm outputs ? programmable filters for fault inputs ? independently programmable pwm output polarity ? independent top and bottom deadtime insertion ? each complementary pair can operate with its own pwm frequency and deadtime values ? individual software control for each pwm output ? all outputs can be forced to a value simultaneously ? pwmx pin can optionally output a third signal from each channel ? channels not used for pwm generation can be used for buffered output compare functions ? channels not used for pwm generation can be used for input capture functions ? enhanced dual edge capture functionality ? option to supply the source for each complementary pwm signal pair from any of the following: ? external digital pin ? internal timer channel ? external adc input, taking into account values set in adc high- and low-limit registers ? dma support
docid023953 rev 4 27/126 spc56xl70lx introduction 125 1.5.31 etimer module the spc56xl70 provides two etimer modules on the lqfp144 package. six 16-bit general purpose up/down timer/counters per module are implemented with the following features: ? maximum clock frequency of 120 mhz ? individual channel capability ? input capture trigger ? output compare ? double buffer (to capture rising edge and falling edge) ? separate prescaler for each counter ? selectable clock source ? 0?100% pulse measurement ? rotation direction flag (quad decoder mode) ? maximum count rate ? equals peripheral clock divided by 2 for external event counting ? equals peripheral clock for internal clock counting ? cascadeable counters ? programmable count modulo ? quadrature decode capabilities ? counters can share available input pins ? count once or repeatedly ? preloadable counters ? pins available as gpio when timer functionality not in use ? dma support 1.5.32 sine wave generator (swg) a digital-to-analog converter is available to generate a sine wave based on 32 stored values for external devices (ex: resolver). ? frequency range from 1 khz to 50 khz ? sine wave amplitude from 0.47 v to 2.26 v
introduction spc56xl70lx 28/126 docid023953 rev 4 1.5.33 analog-to-digital converter module (adc) the adc module features include: analog part: ? 2 on-chip adcs ? 12-bit resolution sar architecture ? same digital interface as in the spc560p family ? a/d channels: 9 external, 3 internal and 4 shared with other a/d (total 16 channels) ? one channel dedicated to each t-sensor to enable temperature reading during application ? separated reference for each adc ? shared analog supply voltage for both adcs ? one sample and hold unit per adc ? adjustable sampling and conversion time digital part: ? 4 analog watchdogs comparing adc results against predefined levels (low, high, range) before results are stored in the appropriate adc result location ? 2 modes of operation: cpu mode or ctu mode ? cpu mode features ? register based interface with the cpu: one result register per channel ? adc state machine managing three request flows: regular command, hardware injected command, software injected command ? selectable priority between software and hardware injected commands ? 4 analog watchdogs comparing adc results against predefined levels (low, high, range) ? dma compatible interface ? ctu mode features ? triggered mode only ? 4 independent result queues (1 16 entries, 2 8 entries, 1 4 entries) ? result alignment circuitry (left justified; right justified) ? 32-bit read mode allows to have channel id on one of the 16-bit parts ? dma compatible interfaces ? built-in self-test features triggered by software 1.5.34 cross triggering unit (ctu) the adc cross triggering unit allows automatic generation of adc conversion requests on user selected conditions without cpu load during the pwm period and with minimized cpu load for dynamic configuration.
docid023953 rev 4 29/126 spc56xl70lx introduction 125 the ctu implements the following features: ? cross triggering between adc, flexpwm, etimer, and external pins ? double buffered trigger generation unit with as many as 8 independent triggers generated from external triggers ? maximum operating frequency less than or equal to 120 mhz ? trigger generation unit configurable in sequential mode or in triggered mode ? trigger delay unit to compensate the delay of external low pass filter ? double buffered global trigger unit allowing etimer synchronization and/or adc command generation ? double buffered adc command list pointers to minimize adc-trigger unit update ? double buffered adc conversion command list with as many as 24 adc commands ? each trigger capable of generating consecutive commands ? adc conversion command allows control of adc channel from each adc, single or synchronous sampling, independent result queue selection ? dma support with safety features 1.5.35 cyclic redundancy checker (crc) unit the crc module is a configurable multiple data flow unit to compute crc signatures on data written to its input register. the crc unit has the following features: ? 3 sets of registers to allow 3 concurrent contexts with possibly different crc computations, each with a selectable polynomial and seed ? computes 16- or 32-bit wide crc on the fl y (single-cycle computation) and stores result in internal register. the following standard crc polynomials are implemented: ? x 8 + x 4 + x 3 + x 2 + 1 [8-bit crc] ? x 16 + x 12 + x 5 + 1 [16-bit crc-ccitt] ? x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x +1 [32-bit crc-ethernet(32)] ? key engine to be coupled with communication periphery where crc application is added to allow implementation of safe communication protocol ? offloads core from cycle-consuming crc and helps checking configuration signature for safe start-up or periodic procedures ? crc unit connected as peripheral bus on internal peripheral bus ? dma support 1.5.36 redundancy control and checker unit (rccu) the rccu checks all outputs of the sphere of replication (addresses, data, control signals). it has the following features: ? duplicated module to guarantee highest possible diagnostic coverage (check of checker) ? multiple times replicated ips are used as checkers on the sor outputs
introduction spc56xl70lx 30/126 docid023953 rev 4 1.5.37 junction temperature sensor the junction temperature sensor provides a value via an adc channel that can be used by software to calculate the device junction temperature. the key parameters of the junction temperature sensor include: ? nominal temperature range from ?40 to 150 c ? software temperature alarm via analog adc comparator possible 1.5.38 nexus port controller (npc) the npc module provides real-time development support capabilities for this device in compliance with the ieee-isto 5001-2008 standard. this development support is supplied for mcus without requiring external address and data pins for internal visibility. the npc block interfaces to the host processor and internal buses to provide development support as per the ieee-isto 5001-2008 class 3+, including selected features from class 4 standard. the development support provided includes program trace, data trace, watchpoint trace, ownership trace, run-time access to the mcus internal memory map and access to the power architecture internal registers during halt. the nexus interface also supports a jtag only mode using only the jtag pins. the following features are implemented: ? full and reduced port modes ? mcko (message clock out) pin ? 4 or 12 mdo (message data out) pins (b) ? 2 mseo (message start/end out) pins ? evto (event out) pin ? auxiliary input port ? evti (event in) pin ? 5-pin jtag port (jcomp, tdi, tdo, tms, and tck) ? supports jtag mode ? host processor (e200) development support features ? data trace via data write messaging (dwm) and data read messaging (drm). this allows the development tool to trace reads or writes, or both, to selected internal memory resources. ? ownership trace via ownership trace messaging (otm). otm facilitates ownership trace by providing visibility of which process id or operating system task is activated. an ownership trace message is transmitted when a new process/task is activated, allowing development tools to trace ownership flow. ? program trace via branch trace messaging (btm). branch trace messaging displays program flow discontinuities (direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. thus, static code may be traced. ? watchpoint messaging (wpm) via the auxiliary port b. 4 mdo pins on lqfp144 package
docid023953 rev 4 31/126 spc56xl70lx introduction 125 ? watchpoint trigger enable of program and/or data trace messaging ? data tracing of instruction fetches via private opcodes 1.5.39 ieee 1149.1 jtag controller (jtagc) the jtagc block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. all data input to and output from the jtagc block is communicated in serial format. the jtagc block is compliant with the ieee standard. the jtag controller provides the following features: ? ieee test access port (tap) interface with 5 pins: ?tdi ?tms ?tck ?tdo ?jcomp ? selectable modes of operation include jtagc/debug or normal system operation ? 5-bit instruction register that supports the following ieee 1149.1-2001 defined instructions: ? bypass ? idcode ?extest ? sample ? sample/preload ? 3 test data registers: a bypass register, a boundary scan register, and a device identification register. the size of the boundary scan register is parameterized to support a variety of boundary scan chain lengths. ? tap controller state machine that controls the operation of the data registers, instruction register and associated circuitry 1.5.40 voltage regulator / power management unit (pmu) the on-chip voltage regulator module provides the following features: ? single external rail required ? single high supply required: nominal 3.3 v both for packaged and known good die option ? packaged option requires external ballast transistor due to reduced dissipation capacity at high temperature but can use embedded transistor if power dissipation is maintained within package dissipation capacity (lower frequency of operation) ? known good die option uses embedded ballast transistor as dissipation capacity is increased to reduce system cost ? all i/os are at same voltage as external supply (3.3 v nominal) ? duplicated low-voltage detectors (lvd) to guarantee proper operation at all stages (reset, configuration, normal operation) and, to maximize safety coverage, one lvd can be tested while the other operates (on-line self-testing feature)
introduction spc56xl70lx 32/126 docid023953 rev 4 1.5.41 built-in self-t est (bist) capability this device includes the following protection against latent faults: ? boot-time memory built-in self-test (mbist) ? boot-time scan-based logic built-in self-test (lbist) ? run-time adc built-in self-test (bist) ? run-time built-in self test of lvds
docid023953 rev 4 33/126 spc56xl70lx package pinouts and signal descriptions 125 2 package pinouts and signal descriptions 2.1 package pinouts figure 2 shows the spc56xl70 in the lqfp100 package. figure 2. spc56xl70 lqfp100 package 1 2 3 4 5 6 7 8 7 5 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 2 6 2 7 2 8 2 9 3 0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 nmi a[6] d[1] a[7] c[4] a[8] c[5] a[5] c[7] vdd_hv_reg_0 vss_lv_cor vdd_lv_cor vdd_hv_io vss_hv_io d[9] vdd_hv_osc vss_hv_osc xtal extal reset d[8] d[5] d[6] vss_lv_pll0_pll1 vdd_lv_pll0_pll1 a[4] vpp_test d[14] c[14] c[13] d[12] vdd_hv_fla vss_hv_fla vdd_hv_reg_1 vss_lv_cor vdd_lv_cor a[3] vdd_hv_io vss_hv_io b[4] tck tms b[5] a[2] c[12] c[11] d[11] d[10] a[1] a[0] d[7] fccu_f[0] vdd_lv_cor vss_lv_cor b[7] b[8] e[2] vdd_hv_adr0 vss_hv_adr0 b[9] b[10] b[11] b[12] vdd_hv_adr1 vss_hv_adr1 vdd_hv_adv vss_hv_adv b[13] b[14] c[0] e[0] bctrl vdd_lv_cor vss_lv_cor vdd_hv_pmu a[15] a[14] c[6] fccu_f[1] b[6] a[13] a[9] vss_lv_cor vdd_lv_cor vdd_hv_reg_2 d[4] d[3] vss_hv_io vdd_hv_io d[0] c[15] jcomp a[12] a[11] a[10] b[3] b[2] c[10] b[1] b[0] lqfp100 package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 lqfp100 package
package pinouts and signal descriptions spc56xl70lx 34/126 docid023953 rev 4 figure 3 shows the spc56xl70 in the lqfp144 package. figure 3. spc56xl70 lqfp144 pinout (top view) ta ble 3 and table 4 provides the pin function summaries for the 100-pin and 144-pin packages respectively, listing all the signals multiplexed to each pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 nmi a[6] d[1] f[4] f[5] vdd_hv_io vss_hv_io f[6] mdo0 a[7] c[4] a[8] c[5] a[5] c[7] vdd_hv_reg_0 vss_lv_cor vdd_lv_cor f[7] f[8] vdd_hv_io vss_hv_io f[9] f[10] f[11] d[9] vdd_hv_osc vss_hv_osc xtal extal reset d[8] d[5] d[6] vss_lv_pll0_pll1 vdd_lv_pll0_pll1 a[4] vpp_test f[12] d[14] g[3] c[14] g[2] c[13] g[4] d[12] g[6] vdd_hv_fla vss_hv_fla vdd_hv_reg_1 vss_lv_cor vdd_lv_cor a[3] vdd_hv_io vss_hv_io b[4] tck tms b[5] g[5] a[2] g[7] c[12] g[8] c[11] g[9] d[11] g[10] d[10] g[11] a[1] a[0] d[7] fccu_f[0] vdd_lv_cor vss_lv_cor c[1] e[4] b[7] e[5] c[2] e[6] b[8] e[7] e[2] vdd_hv_adr0 vss_hv_adr0 b[9] b[10] b[11] b[12] vdd_hv_adr1 vss_hv_adr1 vdd_hv_adv vss_hv_adv b[13] e[9] b[15] e[10] b[14] e[11] c[0] e[12] e[0] bctrl vdd_lv_cor vss_lv_cor vdd_hv_pmu a[15] a[14] c[6] fccu_f[1] d[2] f[3] b[6] vss_lv_cor a[13] vdd_lv_cor a[9] f[0] vss_lv_cor vdd_lv_cor vdd_hv_reg_2 d[4] d[3] vss_hv_io vdd_hv_io d[0] c[15] jcomp a[12] e[15] a[11] e[14] a[10] e[13] b[3] f[14] b[2] f[15] f[13] c[10] b[1] b[0] lqfp144 package table 3. lqfp100 pin function summary pin # port/function peripheral output function input function 1nmi ? 2a[6] siul gpio[6] gpio[6] dspi_1 sck sck siul ? eirq[6] 3d[1] siul gpio[49] gpio[49] etimer_1 etc[2] etc[2] ctu_0 ext_tgr ? flexray ? ca_rx
docid023953 rev 4 35/126 spc56xl70lx package pinouts and signal descriptions 125 4a[7] siul gpio[7] gpio[7] dspi_1 sout ? siul ? eirq[7] flexcan_2 ? rxd 5c[4] siul gpio[36] gpio[36] dspi_0 cs0 cs0 flexpwm_0 x[1] x[1] sscm debug[4] ? siul ? eirq[22] 6a[8] siul gpio[8] gpio[8] dspi_1 ? sin siul ? eirq[8] flexcan_2 txd ? 7c[5] siul gpio[37] gpio[37] dspi_0 sck sck sscm debug[5] ? flexpwm_0 ? fault[3] siul ? eirq[23] 8a[5] siul gpio[5] gpio[5] dspi_1 cs0 cs0 etimer_1 etc[5] etc[5] dspi_0 cs7 ? siul ? eirq[5] 9c[7] siul gpio[39] gpio[39] flexpwm_0 a[1] a[1] sscm debug[7] ? dspi_0 ? sin 10 v dd_hv_reg_0 ? 11 v ss_lv_cor ? 12 v dd_lv_cor ? 13 v dd_hv_io ? 14 v ss_hv_io ? 15 d[9] siul gpio[57] gpio[57] flexpwm_0 x[0] x[0] linflexd_1 txd ? table 3. lqfp100 pin function summary (continued) pin # port/function peripheral output function input function
package pinouts and signal descriptions spc56xl70lx 36/126 docid023953 rev 4 16 v dd_hv_osc ? 17 v ss_hv_osc ? 18 xtalin ? 19 xtalout ? 20 reset ? 21 d[8] siul gpio[56] gpio[56] dspi_1 cs2 ? etimer_1 etc[4] etc[4] dspi_0 cs5 ? flexpwm_0 ? fault[3] 22 d[5] siul gpio[53] gpio[53] dspi_0 cs3 ? flexpwm_0 ? fault[2] 23 d[6] siul gpio[54] gpio[54] dspi_0 cs2 ? flexpwm_0 x[3] x[3] flexpwm_0 ? fault[1] 24 v ss_lv_pll0_pll1 ? 25 v dd_lv_pll0_pll1 ? 26 d[7] siul gpio[55] gpio[55] dspi_1 cs3 ? dspi_0 cs4 ? swg analog output ? 27 fccu_f[0] fccu f[0] f[0] 28 v dd_lv_cor ? 29 v ss_lv_cor ? 30 b[7] siul ? gpio[23] linflexd_0 ? rxd adc_0 ? an[0] 31 b[8] siul ? gpio[24] etimer_0 ? etc[5] adc_0 ? an[1] 32 e[2] siul ? gpio[66] adc_0 ? an[5] 33 v dd_hv_adr0 ? table 3. lqfp100 pin function summary (continued) pin # port/function peripheral output function input function
docid023953 rev 4 37/126 spc56xl70lx package pinouts and signal descriptions 125 34 v ss_hv_adr0 ? 35 b[9] siul ? gpio[25] adc_0 ?an[11] adc_1 36 b[10] siul ? gpio[26] adc_0 ?an[12] adc_1 37 b[11] siul ? gpio[27] adc_0 ?an[13] adc_1 38 b[12] siul ? gpio[28] adc_0 ?an[14] adc_1 39 v dd_hv_adr1 ? 40 v ss_hv_adr1 ? 41 v dd_hv_adv ? 42 v ss_hv_adv ? 43 b[13] siul ? gpio[29] linflexd_1 ? rxd adc_1 ? an[0] 44 b[14] siul ? gpio[30] etimer_0 ? etc[4] siul ? eirq[19] adc_1 ? an[1] 45 c[0] siul ? gpio[32] adc_1 ? an[3] 46 e[0] siul ? gpio[64] adc_1 ? an[5] 47 bctrl ? 48 v dd_lv_cor ? 49 v ss_lv_cor ? 50 v dd_hv_pmu ? table 3. lqfp100 pin function summary (continued) pin # port/function peripheral output function input function
package pinouts and signal descriptions spc56xl70lx 38/126 docid023953 rev 4 51 a[0] siul gpio[0] gpio[0] etimer_0 etc[0] etc[0] dspi_2 sck sck siul ? eirq[0] 52 a[1] siul gpio[1] gpio[1] etimer_0 etc[1] etc[1] dspi_2 sout ? siul ? eirq[1] 53 d[10] siul gpio[58] gpio[58] flexpwm_0 a[0] a[0] etimer_0 ? etc[0] 54 d[11] siul gpio[59] gpio[59] flexpwm_0 b[0] b[0] etimer_0 ? etc[1] 55 c[11] siul gpio[43] gpio[43] etimer_0 etc[4] etc[4] dspi_2 cs2 ? 56 c[12] siul gpio[44] gpio[44] etimer_0 etc[5] etc[5] dspi_2 cs3 ? 57 a[2] siul gpio[2] gpio[2] etimer_0 etc[2] etc[2] flexpwm_0 a[3] a[3] dspi_2 ? sin mc_rgm ? abs[0] siul ? eirq[2] 58 b[5] siul gpio[21] gpio[21] jtagc ? tdi 59 tms ? 60 tck ? 61 b[4] siul gpio[20] gpio[20] jtagc tdo ? 62 v ss_hv_io ? 63 v dd_hv_io ? table 3. lqfp100 pin function summary (continued) pin # port/function peripheral output function input function
docid023953 rev 4 39/126 spc56xl70lx package pinouts and signal descriptions 125 64 a[3] siul gpio[3] gpio[3] etimer_0 etc[3] etc[3] dspi_2 cs0 cs0 flexpwm_0 b[3] b[3] mc_rgm ? abs[2] siul ? eirq[3] 65 v dd_lv_cor ? 66 v ss_lv_cor ? 67 v dd_hv_reg_1 ? 68 v ss_hv_fla ? 69 v dd_hv_fla ? 70 d[12] siul gpio[60] gpio[60] flexpwm_0 x[1] x[1] linflexd_1 ? rxd 71 c[13] siul gpio[45] gpio[45] etimer_1 etc[1] etc[1] ctu_0 ? ext_in flexpwm_0 ? ext_sync 72 c[14] siul gpio[46] gpio[46] etimer_1 etc[2] etc[2] ctu_0 ext_tgr ? 73 d[14] siul gpio[62] gpio[62] flexpwm_0 b[1] b[1] etimer_0 ? etc[3] 74 v pp_test (1) ? 75 a[4] siul gpio[4] gpio[4] etimer_1 etc[0] etc[0] dspi_2 cs1 ? etimer_0 etc[4] etc[4] mc_rgm ? fab siul ? eirq[4] table 3. lqfp100 pin function summary (continued) pin # port/function peripheral output function input function
package pinouts and signal descriptions spc56xl70lx 40/126 docid023953 rev 4 76 b[0] siul gpio[16] gpio[16] flexcan_0 txd ? etimer_1 etc[2] etc[2] sscm debug[0] ? siul ? eirq[15] 77 b[1] siul gpio[17] gpio[17] etimer_1 etc[3] etc[3] sscm debug[1] ? flexcan_0 ? rxd flexcan_1 ? rxd siul ? eirq[16] 78 c[10] siul gpio[42] gpio[42] dspi_2 cs2 ? flexpwm_0 a[3] a[3] flexpwm_0 ? fault[1] 79 b[2] siul gpio[18] gpio[18] linflexd_0 txd ? sscm debug[2] debug[2] siul ? eirq[17] 80 b[3] siul gpio[19] gpio[19] sscm debug[3] debug[3] linflexd_0 ? rxd 81 a[10] siul gpio[10] gpio[10] dspi_2 cs0 cs0 flexpwm_0 b[0] b[0] flexpwm_0 x[2] x[2] siul ? eirq[9] 82 a[11] siul gpio[11] gpio[11] dspi_2 sck sck flexpwm_0 a[0] a[0] flexpwm_0 a[2] a[2] siul ? eirq[10] table 3. lqfp100 pin function summary (continued) pin # port/function peripheral output function input function
docid023953 rev 4 41/126 spc56xl70lx package pinouts and signal descriptions 125 83 a[12] siul gpio[12] gpio[12] dspi_2 sout ? flexpwm_0 a[2] a[2] flexpwm_0 b[2] b[2] siul ? eirq[11] 84 jcomp ? ? jcomp 85 c[15] siul gpio[47] gpio[47] flexray ca_tr_en ? etimer_1 etc[0] etc[0] flexpwm_0 a[1] a[1] ctu_0 ? ext_in flexpwm_0 ? ext_sync 86 d[0] siul gpio[48] gpio[48] flexray ca_tx ? etimer_1 etc[1] etc[1] flexpwm_0 b[1] b[1] 87 v dd_hv_io ? 88 v ss_hv_io ? 89 d[3] siul gpio[51] gpio[51] flexray cb_tx ? etimer_1 etc[4] etc[4] flexpwm_0 a[3] a[3] 90 d[4] siul gpio[52] gpio[52] flexray cb_tr_en ? etimer_1 etc[5] etc[5] flexpwm_0 b[3] b[3] 91 v dd_hv_reg_2 ? 92 v dd_lv_cor ? 93 v ss_lv_cor ? 94 a[9] siul gpio[9] gpio[9] dspi_2 cs1 ? flexpwm_0 b[3] b[3] flexpwm_0 ? fault[0] table 3. lqfp100 pin function summary (continued) pin # port/function peripheral output function input function
package pinouts and signal descriptions spc56xl70lx 42/126 docid023953 rev 4 95 a[13] siul gpio[13] gpio[13] flexpwm_0 b[2] b[2] dspi_2 ? sin flexpwm_0 ? fault[0] siul ? eirq[12] 96 b[6] siul gpio[22] gpio[22] mc_cgm clk_out ? dspi_2 cs2 ? siul ? eirq[18] 97 fccu_f[1] fccu f[1] f[1] 98 c[6] siul gpio[38] gpio[38] dspi_0 sout ? flexpwm_0 b[1] b[1] sscm debug[6] ? siul ? eirq[24] 99 a[14] siul gpio[14] gpio[14] flexcan_1 txd ? etimer_1 etc[4] etc[4] siul ? eirq[13] 100 a[15] siul gpio[15] gpio[15] etimer_1 etc[5] etc[5] flexcan_1 ? rxd flexcan_0 ? rxd siul ? eirq[14] 1. v pp_test should always be tied to ground (v ss ) for normal operations. table 4. lqfp144 pin function summary pin # port/function peripheral output function input function 1nmi ? 2a[6] siul gpio[6] gpio[6] dspi_1 sck sck siul ? eirq[6] table 3. lqfp100 pin function summary (continued) pin # port/function peripheral output function input function
docid023953 rev 4 43/126 spc56xl70lx package pinouts and signal descriptions 125 3d[1] siul gpio[49] gpio[49] etimer_1 etc[2] etc[2] ctu_0 ext_tgr ? flexray ? ca_rx 4f[4] siul gpio[84] gpio[84] npc mdo[3] ? 5f[5] siul gpio[85] gpio[85] npc mdo[2] ? 6v dd_hv_io ? 7v ss_hv_io ? 8f[6] siul gpio[86] gpio[86] npc mdo[1] ? 9mdo0 ? 10 a[7] siul gpio[7] gpio[7] dspi_1 sout ? siul ? eirq[7] flexcan_2 ? rxd 11 c[4] siul gpio[36] gpio[36] dspi_0 cs0 cs0 flexpwm_0 x[1] x[1] sscm debug[4] ? siul ? eirq[22] 12 a[8] siul gpio[8] gpio[8] dspi_1 ? sin siul ? eirq[8] flexcan_2 txd ? 13 c[5] siul gpio[37] gpio[37] dspi_0 sck sck sscm debug[5] ? flexpwm_0 ? fault[3] siul ? eirq[23] table 4. lqfp144 pin function summary (continued) pin # port/function peripheral output function input function
package pinouts and signal descriptions spc56xl70lx 44/126 docid023953 rev 4 14 a[5] siul gpio[5] gpio[5] dspi_1 cs0 cs0 etimer_1 etc[5] etc[5] dspi_0 cs7 ? siul ? eirq[5] 15 c[7] siul gpio[39] gpio[39] flexpwm_0 a[1] a[1] sscm debug[7] ? dspi_0 ? sin 16 v dd_hv_reg_0 ? 17 v ss_lv_cor ? 18 v dd_lv_cor ? 19 f[7] siul gpio[87] gpio[87] npc mcko ? 20 f[8] siul gpio[88] gpio[88] npc mseo[1] ? 21 v dd_hv_io ? 22 v ss_hv_io ? 23 f[9] siul gpio[89] gpio[89] npc mseo[0] ? 24 f[10] siul gpio[90] gpio[90] npc evto ? 25 f[11] siul gpio[91] gpio[91] npc evti ? 26 d[9] siul gpio[57] gpio[57] flexpwm_0 x[0] x[0] linflexd_1 txd ? 27 v dd_hv_osc ? 28 v ss_hv_osc ? 29 xtalin ? 30 xtalout ? 31 reset ? table 4. lqfp144 pin function summary (continued) pin # port/function peripheral output function input function
docid023953 rev 4 45/126 spc56xl70lx package pinouts and signal descriptions 125 32 d[8] siul gpio[56] gpio[56] dspi_1 cs2 ? etimer_1 etc[4] etc[4] dspi_0 cs5 ? flexpwm_0 ? fault[3] 33 d[5] siul gpio[53] gpio[53] dspi_0 cs3 ? flexpwm_0 ? fault[2] 34 d[6] siul gpio[54] gpio[54] dspi_0 cs2 ? flexpwm_0 x[3] x[3] flexpwm_0 ? fault[1] 35 v ss_lv_pll0_pll1 ? 36 v dd_lv_pll0_pll1 ? 37 d[7] siul gpio[55] gpio[55] dspi_1 cs3 ? dspi_0 cs4 ? swg analog output ? 38 fccu_f[0] fccu f[0] f[0] 39 v dd_lv_cor ? 40 v ss_lv_cor ? 41 c[1] siul ? gpio[33] adc_0 ? an[2] 42 e[4] siul ? gpio[68] adc_0 ? an[7] 43 b[7] siul ? gpio[23] linflexd_0 ? rxd adc_0 ? an[0] 44 e[5] siul ? gpio[69] adc_0 ? an[8] 45 c[2] siul ? gpio[34] adc_0 ? an[3] 46 e[6] siul ? gpio[70] adc_0 ? an[4] table 4. lqfp144 pin function summary (continued) pin # port/function peripheral output function input function
package pinouts and signal descriptions spc56xl70lx 46/126 docid023953 rev 4 47 b[8] siul ? gpio[24] etimer_0 ? etc[5] adc_0 ? an[1] 48 e[7] siul ? gpio[71] adc_0 ? an[6] 49 e[2] siul ? gpio[66] adc_0 ? an[5] 50 v dd_hv_adr0 ? 51 v ss_hv_adr0 ? 52 b[9] siul ? gpio[25] adc_0 adc_1 ?an[11] 53 b[10] siul ? gpio[26] adc_0 adc_1 ?an[12] 54 b[11] siul ? gpio[27] adc_0 adc_1 ?an[13] 55 b[12] siul ? gpio[28] adc_0 adc_1 ?an[14] 56 v dd_hv_adr1 ? 57 v ss_hv_adr1 ? 58 v dd_hv_adv ? 59 v ss_hv_adv ? 60 b[13] siul ? gpio[29] linflexd_1 ? rxd adc_1 ? an[0] 61 e[9] siul ? gpio[73] adc_1 ? an[7] 62 b[15] siul ? gpio[31] siul ? eirq[20] adc_1 ? an[2] 63 e[10] siul ? gpio[74] adc_1 ? an[8] table 4. lqfp144 pin function summary (continued) pin # port/function peripheral output function input function
docid023953 rev 4 47/126 spc56xl70lx package pinouts and signal descriptions 125 64 b[14] siul ? gpio[30] etimer_0 ? etc[4] siul ? eirq[19] adc_1 ? an[1] 65 e[11] siul ? gpio[75] adc_1 ? an[4] 66 c[0] siul ? gpio[32] adc_1 ? an[3] 67 e[12] siul ? gpio[76] adc_1 ? an[6] 68 e[0] siul ? gpio[64] adc_1 ? an[5] 69 bctrl ? 70 v dd_lv_cor ? 71 v ss_lv_cor ? 72 v dd_hv_pmu ? 73 a[0] siul gpio[0] gpio[0] etimer_0 etc[0] etc[0] dspi_2 sck sck siul ? eirq[0] 74 a[1] siul gpio[1] gpio[1] etimer_0 etc[1] etc[1] dspi_2 sout ? siul ? eirq[1] 75 g[11] siul gpio[107] gpio[107] flexray dbg3 ? flexpwm_0 ? fault[3] 76 d[10] siul gpio[58] gpio[58] flexpwm_0 a[0] a[0] etimer_0 ? etc[0] 77 g[10] siul gpio[106] gpio[106] flexray dbg2 ? dspi_2 cs3 ? flexpwm_0 ? fault[2] table 4. lqfp144 pin function summary (continued) pin # port/function peripheral output function input function
package pinouts and signal descriptions spc56xl70lx 48/126 docid023953 rev 4 78 d[11] siul gpio[59] gpio[59] flexpwm_0 b[0] b[0] etimer_0 ? etc[1] 79 g[9] siul gpio[105] gpio[105] flexray dbg1 ? dspi_1 cs1 ? flexpwm_0 ? fault[1] siul ? eirq[29] 80 c[11] siul gpio[43] gpio[43] etimer_0 etc[4] etc[4] dspi_2 cs2 ? 81 g[8] siul gpio[104] gpio[104] flexray dbg0 ? dspi_0 cs1 ? flexpwm_0 ? fault[0] siul ? eirq[21] 82 c[12] siul gpio[44] gpio[44] etimer_0 etc[5] etc[5] dspi_2 cs3 ? 83 g[7] siul gpio[103] gpio[103] flexpwm_0 b[3] b[3] 84 a[2] siul gpio[2] gpio[2] etimer_0 etc[2] etc[2] flexpwm_0 a[3] a[3] dspi_2 ? sin mc_rgm ? abs[0] siul ? eirq[2] 85 g[5] siul gpio[101] gpio[101] flexpwm_0 x[3] x[3] dspi_2 cs3 ? 86 b[5] siul gpio[21] gpio[21] jtagc ? tdi 87 tms ? 88 tck ? table 4. lqfp144 pin function summary (continued) pin # port/function peripheral output function input function
docid023953 rev 4 49/126 spc56xl70lx package pinouts and signal descriptions 125 89 b[4] siul gpio[20] gpio[20] jtagc tdo ? 90 v ss_hv_io ? 91 v dd_hv_io ? 92 a[3] siul gpio[3] gpio[3] etimer_0 etc[3] etc[3] dspi_2 cs0 cs0 flexpwm_0 b[3] b[3] mc_rgm ? abs[2] siul ? eirq[3] 93 v dd_lv_cor ? 94 v ss_lv_cor ? 95 v dd_hv_reg_1 ? 96 v ss_hv_fla ? 97 v dd_hv_fla ? 98 g[6] siul gpio[102] gpio[102] flexpwm_0 a[3] a[3] 99 d[12] siul gpio[60] gpio[60] flexpwm_0 x[1] x[1] linflexd_1 ? rxd 100 g[4] siul gpio[100] gpio[100] flexpwm_0 b[2] b[2] etimer_0 ? etc[5] 101 c[13] siul gpio[45] gpio[45] etimer_1 etc[1] etc[1] ctu_0 ? ext_in flexpwm_0 ? ext_sync 102 g[2] siul gpio[98] gpio[98] flexpwm_0 x[2] x[2] dspi_1 cs1 ? 103 c[14] siul gpio[46] gpio[46] etimer_1 etc[2] etc[2] ctu_0 ext_tgr ? table 4. lqfp144 pin function summary (continued) pin # port/function peripheral output function input function
package pinouts and signal descriptions spc56xl70lx 50/126 docid023953 rev 4 104 g[3] siul gpio[99] gpio[99] flexpwm_0 a[2] a[2] etimer_0 ? etc[4] 105 d[14] siul gpio[62] gpio[62] flexpwm_0 b[1] b[1] etimer_0 ? etc[3] 106 f[12] siul gpio[92] gpio[92] etimer_1 etc[3] etc[3] siul ? eirq[30] 107 v pp_test (1) ? 108 a[4] siul gpio[4] gpio[4] etimer_1 etc[0] etc[0] dspi_2 cs1 ? etimer_0 etc[4] etc[4] mc_rgm ? fab siul ? eirq[4] 109 b[0] siul gpio[16] gpio[16] flexcan_0 txd ? etimer_1 etc[2] etc[2] sscm debug[0] ? siul ? eirq[15] 110 b[1] siul gpio[17] gpio[17] etimer_1 etc[3] etc[3] sscm debug[1] ? flexcan_0 ? rxd flexcan_1 ? rxd siul ? eirq[16] 111 c[10] siul gpio[42] gpio[42] dspi_2 cs2 ? flexpwm_0 a[3] a[3] flexpwm_0 ? fault[1] 112 f[13] siul gpio[93] gpio[93] etimer_1 etc[4] etc[4] siul ? eirq[31] table 4. lqfp144 pin function summary (continued) pin # port/function peripheral output function input function
docid023953 rev 4 51/126 spc56xl70lx package pinouts and signal descriptions 125 113 f[15] siul gpio[95] gpio[95] linflexd_1 ? rxd flexcan_2 txd ? 114 b[2] siul gpio[18] gpio[18] linflexd_0 txd ? sscm debug[2] ? siul ? eirq[17] 115 f[14] siul gpio[94] gpio[94] linflexd_1 txd ? flexcan_2 ? rxd 116 b[3] siul gpio[19] gpio[19] sscm debug[3] ? linflexd_0 ? rxd 117 e[13] siul gpio[77] gpio[77] etimer_0 etc[5] etc[5] dspi_2 cs3 ? siul ? eirq[25] 118 a[10] siul gpio[10] gpio[10] dspi_2 cs0 cs0 flexpwm_0 b[0] b[0] flexpwm_0 x[2] x[2] siul ? eirq[9] 119 e[14] siul gpio[78] gpio[78] etimer_1 etc[5] etc[5] siul ? eirq[26] 120 a[11] siul gpio[11] gpio[11] dspi_2 sck sck flexpwm_0 a[0] a[0] flexpwm_0 a[2] a[2] siul ? eirq[10] 121 e[15] siul gpio[79] gpio[79] dspi_0 cs1 ? siul ? eirq[27] table 4. lqfp144 pin function summary (continued) pin # port/function peripheral output function input function
package pinouts and signal descriptions spc56xl70lx 52/126 docid023953 rev 4 122 a[12] siul gpio[12] gpio[12] dspi_2 sout ? flexpwm_0 a[2] a[2] flexpwm_0 b[2] b[2] siul ? eirq[11] 123 jcomp ? ? jcomp 124 c[15] siul gpio[47] gpio[47] flexray ca_tr_en ? etimer_1 etc[0] etc[0] flexpwm_0 a[1] a[1] ctu_0 ? ext_in flexpwm_0 ? ext_sync 125 d[0] siul gpio[48] gpio[48] flexray ca_tx ? etimer_1 etc[1] etc[1] flexpwm_0 b[1] b[1] 126 v dd_hv_io ? 127 v ss_hv_io ? 128 d[3] siul gpio[51] gpio[51] flexray cb_tx ? etimer_1 etc[4] etc[4] flexpwm_0 a[3] a[3] 129 d[4] siul gpio[52] gpio[52] flexray cb_tr_en ? etimer_1 etc[5] etc[5] flexpwm_0 b[3] b[3] 130 v dd_hv_reg_2 ? 131 v dd_lv_cor ? 132 v ss_lv_cor ? 133 f[0] siul gpio[80] gpio[80] flexpwm_0 a[1] a[1] etimer_0 ? etc[2] siul ? eirq[28] table 4. lqfp144 pin function summary (continued) pin # port/function peripheral output function input function
docid023953 rev 4 53/126 spc56xl70lx package pinouts and signal descriptions 125 134 a[9] siul gpio[9] gpio[9] dspi_2 cs1 ? flexpwm_0 b[3] b[3] flexpwm_0 ? fault[0] 135 v dd_lv_cor ? 136 a[13] siul gpio[13] gpio[13] flexpwm_0 b[2] b[2] dspi_2 ? sin flexpwm_0 ? fault[0] siul ? eirq[12] 137 v ss_lv_cor ? 138 b[6] siul gpio[22] gpio[22] mc_cgm clk_out ? dspi_2 cs2 ? siul ? eirq[18] 139 f[3] siul gpio[83] gpio[83] dspi_0 cs6 ? 140 d[2] siul gpio[50] gpio[50] etimer_1 etc[3] etc[3] flexpwm_0 x[3] x[3] flexray ? cb_rx 141 fccu_f[1] fccu f[1] f[1] 142 c[6] siul gpio[38] gpio[38] dspi_0 sout ? flexpwm_0 b[1] b[1] sscm debug[6] ? siul ? eirq[24] 143 a[14] siul gpio[14] gpio[14] flexcan_1 txd ? etimer_1 etc[4] etc[4] siul ? eirq[13] table 4. lqfp144 pin function summary (continued) pin # port/function peripheral output function input function
package pinouts and signal descriptions spc56xl70lx 54/126 docid023953 rev 4 2.2 supply pins 144 a[15] siul gpio[15] gpio[15] etimer_1 etc[5] etc[5] flexcan_1 ? rxd flexcan_0 ? rxd siul ? eirq[14] 1. v pp_test should always be tied to ground (v ss ) for normal operations. table 4. lqfp144 pin function summary (continued) pin # port/function peripheral output function input function table 5. supply pins supply pin # symbol description 100 pkg 144 pkg vreg control and power supply pins bctrl voltage regulator external npn ballast base control pin 47 69 v dd_lv_cor core logic supply 48 70 v ss_lv_cor core regulator ground 49 71 v dd_hv_pmu voltage regulator supply 50 72 adc_0/adc_1 reference voltage and adc supply v dd_hv_adr0 adc_0 high reference voltage 33 50 v ss_hv_adr0 adc_0 low reference voltage 34 51 v dd_hv_adr1 adc_1 high reference voltage 39 56 v ss_hv_adr1 adc_1 low reference voltage 40 57 v dd_hv_adv adc voltage supply for adc_0 and adc_1 41 58 v ss_hv_adv adc ground for adc_0 and adc_1 42 59 power supply pins (3.3 v) v dd_hv_io 3.3 v input/output supply voltage ? 6 v ss_hv_io 3.3 v input/output ground ? 7 v dd_hv_reg_0 vdd_hv_reg_0 10 16 v dd_hv_io 3.3 v input/output supply voltage 13 21 v ss_hv_io 3.3 v input/output ground 14 22 v dd_hv_osc crystal oscillator amplifier supply voltage 16 27 v ss_hv_osc crystal oscillator amplifier ground 17 28 v ss_hv_io 3.3 v input/output ground 62 90 v dd_hv_io 3.3 v input/output supply voltage 63 91
docid023953 rev 4 55/126 spc56xl70lx package pinouts and signal descriptions 125 v dd_hv_reg_1 vdd_hv_reg_1 67 95 v ss_hv_fla vss_hv_fla 68 96 v dd_hv_fla vdd_hv_fla 69 97 v dd_hv_io vdd_hv_io 87 126 v ss_hv_io vss_hv_io 88 127 v dd_hv_reg_2 vdd_hv_reg_2 91 130 power supply pins (1.2 v) v ss_lv_cor vss_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 11 17 v dd_lv_cor vdd_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor pin. 12 18 v ss 1v2 vss_lv_pll0_pll1 / 1.2 v decoupling pins for on-chip fmpll modules. decoupling capacitor must be connected between this pin and v dd_lv_pll. 24 35 v dd 1v2 vdd_lv_pll0_pll1 decoupling pins for on-chip fmpll modules. decoupling capacitor must be connected between this pin and v ss_lv_pll. 25 36 v dd_lv_cor vdd_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor pin. 28 39 v ss_lv_cor vss_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 29 40 v dd_lv_cor vdd_lv_cor decoupling pins for core logic and regulator feedback. decoupling capacitor must be connected between this pins and v ss_lv_regcor. ?70 v ss_lv_cor vss_lv_regcor0 decoupling pins for core logic and regulator feedback. decoupling capacitor must be connected between this pins and v dd_lv_regcor. ?71 v dd_lv_cor vdd_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor pin. 65 93 v ss_lv_cor vss_lv_cor / 1.2 v decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 66 94 v dd 1v2 vdd_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 92 131 table 5. supply pins (continued) supply pin # symbol description 100 pkg 144 pkg
package pinouts and signal descriptions spc56xl70lx 56/126 docid023953 rev 4 2.3 system pins v ss 1v2 vss_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 93 132 v dd 1v2 vdd_lv_cor / decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. ? 135 v ss 1v2 vss_lv_cor / decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. ? 137 table 5. supply pins (continued) supply pin # symbol description 100 pkg 144 pkg table 6. system pins symbol description direction pin # 100 pkg 144 pkg dedicated pins mdo0 (1) nexus message data output ? line output only ? 9 nmi (2) non maskable interrupt input only 1 1 xtal input for oscillator amplifier circuit and internal clock generator input only 18 29 extal (3) oscillator amplifier output input/output (4) 19 30 tms (2) jtag state machine control input only 59 87 tck (2) jtag clock input only 60 88 jcomp (5) jtag compliance select input only 84 123 reset pin reset bidirectional reset with schmitt-trigger characteristics and noise filter. this pin has medium drive strength. output drive is open drain and must be terminated by an external resistor of value 1kohm. (6) bidirectional 20 31 tes t p i n vpp test pin for testing purpose only. to be tied to ground in normal operating mode. 74 107 1. this pad is configured for fast (f) pad speed. 2. this pad contains a weak pull-up. 3. extal is an "output" in "crystal" mode, and is an "input" in "ext clock" mode. 4. in xosc bypass mode, the analog portion of crystal oscillator (amplifier) is disabled. an external clock can be applied at extal as an input. in xosc normal mode, extal is an output 5. this pad contains a weak pull-down.
docid023953 rev 4 57/126 spc56xl70lx package pinouts and signal descriptions 125 2.4 pin muxing ta ble 7 defines the pin list and muxing for this device. each entry of ta ble 7 shows all the possible configurations for each pin, via the alternate functions. the default function assigned to each pin after reset is indicated by alt0. note: pins labeled ?nc? are to be left unconnected. any connection to an external circuit or voltage may cause unpredictable device behavior or damage. pins labeled ?reserved? are to be tied to ground. not doing so may cause unpredictable device behavior. 6. reset output shall be considered valid only a fter the 3.3v supply reaches its stable value. none of system pins (except reset) provides an open drain output. table 7. pin muxing port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg port a a[0] pcr[0] siul gpio[0] alt0 gpio[0] ? pull down m s 51 73 etimer_0 etc[0] alt1 etc[0] psmi[35]; padsel=0 dspi_2 sck alt2 sck psmi[1]; padsel=0 siul ? ? eirq[0] ? a[1] pcr[1] siul gpio[1] alt0 gpio[1] ? pull down m s 52 74 etimer_0 etc[1] alt1 etc[1] psmi[36]; padsel=0 dspi_2 sout alt2 ? ? siul ? ? eirq[1] ? a[2] pcr[2] siul gpio[2] alt0 gpio[2] ? pull down m s 57 84 etimer_0 etc[2] alt1 etc[2] psmi[37]; padsel=0 flexpwm_0 a[3] alt3 a[3] psmi[23]; padsel=0 dspi_2 ? ? sin psmi[2]; padsel=0 mc_rgm ? ? abs[0] ? siul ? ? eirq[2] ?
package pinouts and signal descriptions spc56xl70lx 58/126 docid023953 rev 4 a[3] pcr[3] siul gpio[3] alt0 gpio[3] ? pull down m s 64 92 etimer_0 etc[3] alt1 etc[3] psmi[38]; padsel=0 dspi_2 cs0 alt2 cs0 psmi[3]; padsel=0 flexpwm_0 b[3] alt3 b[3] psmi[27]; padsel=0 mc_rgm ? ? abs[2] ? siul ? ? eirq[3] ? a[4] pcr[4] siul gpio[4] alt0 gpio[4] ? pull down m s 75 108 etimer_1 etc[0] alt1 etc[0] psmi[9]; padsel=0 dspi_2 cs1 alt2 ? ? etimer_0 etc[4] alt3 etc[4] psmi[7]; padsel=0 mc_rgm ? ? fab ? siul ? ? eirq[4] ? a[5] pcr[5] siul gpio[5] alt0 gpio[5] ? pull down ms814 dspi_1 cs0 alt1 cs0 ? etimer_1 etc[5] alt2 etc[5] psmi[14]; padsel=0 dspi_0 cs7 alt3 ? ? siul ? ? eirq[5] ? a[6] pcr[6] siul gpio[6] alt0 gpio[6] ? pull down ms22 dspi_1 sck alt1 sck ? siul ? ? eirq[6] ? a[7] pcr[7] siul gpio[7] alt0 gpio[7] ? pull down ms410 dspi_1 sout alt1 ? ? siul ? ? eirq[7] ? flexcan_2 rxd alt2 ? ? a[8] pcr[8] siul gpio[8] alt0 gpio[8] ? pull down ms612 dspi_1 ? ? sin ? siul ? ? eirq[8] ? flexcan_2 txd alt2 ? ? table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg
docid023953 rev 4 59/126 spc56xl70lx package pinouts and signal descriptions 125 a[9] pcr[9] siul gpio[9] alt0 gpio[9] ? pull down m s 94 134 dspi_2 cs1 alt1 ? ? flexpwm_0 b[3] alt3 b[3] psmi[27]; padsel=1 flexpwm_0 ? ? fault[0] psmi[16]; padsel=0 a[10] pcr[10] siul gpio[10] alt0 gpio[10] ? pull down ms81118 dspi_2 cs0 alt1 cs0 psmi[3]; padsel=1 flexpwm_0 b[0] alt2 b[0] psmi[24]; padsel=0 flexpwm_0 x[2] alt3 x[2] psmi[29]; padsel=0 siul ? ? eirq[9] ? a[11] pcr[11] siul gpio[11] alt0 gpio[11] ? pull down m s 82 120 dspi_2 sck alt1 sck psmi[1]; padsel=1 flexpwm_0 a[0] alt2 a[0] psmi[20]; padsel=0 flexpwm_0 a[2] alt3 a[2] psmi[22]; padsel=0 siul ? ? eirq[10] ? a[12] pcr[12] siul gpio[12] alt0 gpio[12] ? pull down m s 83 122 dspi_2 sout alt1 ? ? flexpwm_0 a[2] alt2 a[2] psmi[22]; padsel=1 flexpwm_0 b[2] alt3 b[2] psmi[26]; padsel=0 siul ? ? eirq[11] ? table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg
package pinouts and signal descriptions spc56xl70lx 60/126 docid023953 rev 4 a[13] pcr[13] siul gpio[13] alt0 gpio[13] ? pull down m s 95 136 flexpwm_0 b[2] alt2 b[2] psmi[26]; padsel=1 dspi_2 ? ? sin psmi[2]; padsel=1 flexpwm_0 ? ? fault[0] psmi[16]; padsel=1 siul ? ? eirq[12] ? a[14] pcr[14] siul gpio[14] alt0 gpio[14] ? pull down m s 99 143 flexcan_1 txd alt1 ? ? etimer_1 etc[4] alt2 etc[4] psmi[13]; padsel=0 siul ? ? eirq[13] ? a[15] pcr[15] siul gpio[15] alt0 gpio[15] ? pull down m s 100 144 etimer_1 etc[5] alt2 etc[5] psmi[14]; padsel=1 flexcan_1 ? ? rxd psmi[34]; padsel=0 flexcan_0 ? ? rxd psmi[33]; padsel=0 siul ? ? eirq[14] ? port b b[0] pcr[16] siul gpio[16] alt0 gpio[16] ? pull down m s 76 109 flexcan_0 txd alt1 ? ? etimer_1 etc[2] alt2 etc[2] psmi[11]; padsel=0 sscm debug[0] alt3 ? ? siul ? ? eirq[15] ? table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg
docid023953 rev 4 61/126 spc56xl70lx package pinouts and signal descriptions 125 b[1] pcr[17] siul gpio[17] alt0 gpio[17] ? pull down ms77110 etimer_1 etc[3] alt2 etc[3] psmi[12]; padsel=0 sscm debug[1] alt3 ? ? flexcan_0 ? ? rxd psmi[33]; padsel=1 flexcan_1 ? ? rxd psmi[34]; padsel=1 siul ? ? eirq[16] ? b[2] pcr[18] siul gpio[18] alt0 gpio[18] ? pull down ms79114 linflex_0 txd alt1 ? ? sscm debug[2] alt3 ? ? siul ? ? eirq[17] ? b[3] pcr[19] siul gpio[19] alt0 gpio[19] ? pull down ms80116 sscm debug[3] alt3 ? ? linflex_0 ? ? rxd psmi[31]; padsel=0 b[4] (2) pcr[20] siul gpio[20] alt0 gpio[20] ? pull down f s 61 89 jtagc tdo alt1 ? ? b[5] pcr[21] siul gpio[21] alt0 gpio[21] ? pull up m s 58 86 jtagc ? ? tdi ? b[6] pcr[22] siul gpio[22] alt0 gpio[22] ? pull down f s 96 138 mc_cgm clk_out alt1 ? ? dspi_2 cs2 alt2 ? ? siul ? eirq[18] ? b[7] pcr[23] siul ? alt0 gpi[23] ? ???3043 linflex_0 ? ? rxd psmi[31]; padsel=1 adc_0 ? ? an[0] (3) ? b[8] pcr[24] siul ? alt0 gpi[24] ? ???3147 etimer_0 ? ? etc[5] psmi[8]; padsel=2 adc_0 ? ? an[1] (3) ? table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg
package pinouts and signal descriptions spc56xl70lx 62/126 docid023953 rev 4 b[9] pcr[25] siul ? alt0 gpi[25] ? ???3552 adc_0 adc_1 ??an[11] (3) ? b[10] pcr[26] siul ? alt0 gpi[26] ? ???3653 adc_0 adc_1 ??an[12] (3) ? b[11] pcr[27] siul ? alt0 gpi[27] ? ???3754 adc_0 adc_1 ??an[13] (3) ? b[12] pcr[28] siul ? alt0 gpi[28] ? ???3855 adc_0 adc_1 ??an[14] (3) ? b[13] pcr[29] siul ? alt0 gpi[29] ? ???4360 linflex_1 ? ? rxd psmi[32]; padsel=0 adc_1 ? ? an[0] (3) ? b[14] pcr[30] siul ? alt0 gpi[30] ? ???4464 etimer_0 ? ? etc[4] psmi[7]; padsel=2 siul ? ? eirq[19] ? adc_1 ? ? an[1] (3) ? b[15] pcr[31] siul ? alt0 gpi[31] ? ????62 siul ? ? eirq[20] ? adc_1 ? ? an[2] (3) ? port c c[0] pcr[32] siul ? alt0 gpi[32] ? ???4566 adc_1 ? ? an[3] (3) ? c[1] pcr[33] siul ? alt0 gpi[33] ? ????41 adc_0 ? ? an[2] (3) ? c[2] pcr[34] siul ? alt0 gpi[34] ? ????45 adc_0 ? ? an[3] (3) ? table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg
docid023953 rev 4 63/126 spc56xl70lx package pinouts and signal descriptions 125 c[4] pcr[36] siul gpio[36] alt0 gpio[36] ? pull down ms511 dspi_0 cs0 alt1 cs0 ? flexpwm_0 x[1] alt2 x[1] psmi[28]; padsel=0 sscm debug[4] alt3 ? ? siul ? ? eirq[22] ? c[5] pcr[37] siul gpio[37] alt0 gpio[37] ? pull down ms713 dspi_0 sck alt1 sck ? sscm debug[5] alt3 ? ? flexpwm_0 ? ? fault[3] psmi[19]; padsel=0 siul ? ? eirq[23] ? c[6] pcr[38] siul gpio[38] alt0 gpio[38] ? pull down m s 98 142 dspi_0 sout alt1 ? ? flexpwm_0 b[1] alt2 b[1] psmi[25]; padsel=0 sscm debug[6] alt3 ? ? siul ? ? eirq[24] ? c[7] pcr[39] siul gpio[39] alt0 gpio[39] ? pull down ms915 flexpwm_0 a[1] alt2 a[1] psmi[21]; padsel=0 sscm debug[7] alt3 ? ? dspi_0 ? ? sin ? c[10] pcr[42] siul gpio[42] alt0 gpio[42] ? pull down m s 78 111 dspi_2 cs2 alt1 ? ? flexpwm_0 a[3] alt3 a[3] psmi[23]; padsel=1 flexpwm_0 ? ? fault[1] psmi[17]; padsel=0 c[11] pcr[43] siul gpio[43] alt0 gpio[43] ? pull down m s 55 80 etimer_0 etc[4] alt1 etc[4] psmi[7]; padsel=1 dspi_2 cs2 alt2 ? ? table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg
package pinouts and signal descriptions spc56xl70lx 64/126 docid023953 rev 4 c[12] pcr[44] siul gpio[44] alt0 gpio[44] ? pull down m s 56 82 etimer_0 etc[5] alt1 etc[5] psmi[8]; padsel=0 dspi_2 cs3 alt2 ? ? c[13] pcr[45] siul gpio[45] alt0 gpio[45] ? pull down m s 71 101 etimer_1 etc[1] alt1 etc[1] psmi[10]; padsel=0 ctu_0 ? ? ext_in psmi[0]; padsel=0 flexpwm_0 ? ? ext_syn c psmi[15]; padsel=0 c[14] pcr[46] siul gpio[46] alt0 gpio[46] ? pull down m s 72 103 etimer_1 etc[2] alt1 etc[2] psmi[11]; padsel=1 ctu_0 ext_tgr alt2 ? ? c[15] pcr[47] siul gpio[47] alt0 gpio[47] ? pull down sym s 85 124 flexray ca_tr_e n alt1 ? ? etimer_1 etc[0] alt2 etc[0] psmi[9]; padsel=1 flexpwm_0 a[1] alt3 a[1] psmi[21]; padsel=1 ctu_0 ? ? ext_in psmi[0]; padsel=1 flexpwm_0 ? ? ext_syn c psmi[15]; padsel=1 port d d[0] pcr[48] siul gpio[48] alt0 gpio[48] ? pull down sym s 86 125 flexray ca_tx alt1 ? ? etimer_1 etc[1] alt2 etc[1] psmi[10]; padsel=1 flexpwm_0 b[1] alt3 b[1] psmi[25]; padsel=1 table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg
docid023953 rev 4 65/126 spc56xl70lx package pinouts and signal descriptions 125 d[1] pcr[49] siul gpio[49] alt0 gpio[49] ? pull down ms33 etimer_1 etc[2] alt2 etc[2] psmi[11]; padsel=2 ctu_0 ext_tgr alt3 ? ? flexray ? ? ca_rx ? d[2] pcr[50] siul gpio[50] alt0 gpio[50] ? pull down ms?140 etimer_1 etc[3] alt2 etc[3] psmi[12]; padsel=1 flexpwm_0 x[3] alt3 x[3] psmi[30]; padsel=0 flexray ? ? cb_rx ? d[3] pcr[51] siul gpio[51] alt0 gpio[51] ? pull down sym s 89 128 flexray cb_tx alt1 ? ? etimer_1 etc[4] alt2 etc[4] psmi[13]; padsel=1 flexpwm_0 a[3] alt3 a[3] psmi[23]; padsel=2 d[4] pcr[52] siul gpio[52] alt0 gpio[52] ? pull down sym s 90 129 flexray cb_tr_e n alt1 ? ? etimer_1 etc[5] alt2 etc[5] psmi[14]; padsel=2 flexpwm_0 b[3] alt3 b[3] psmi[27]; padsel=2 d[5] pcr[53] siul gpio[53] alt0 gpio[53] ? pull down m s 22 33 dspi_0 cs3 alt1 ? ? flexpwm_0 ? ? fault[2] psmi[18]; padsel=0 d[6] pcr[54] siul gpio[54] alt0 gpio[54] ? pull down m s 23 34 dspi_0 cs2 alt1 ? ? flexpwm_0 x[3] alt3 x[3] psmi[30]; padsel=1 flexpwm_0 ? ? fault[1] psmi[17]; padsel=1 table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg
package pinouts and signal descriptions spc56xl70lx 66/126 docid023953 rev 4 d[7] pcr[55] siul gpio[55] alt0 gpio[55] ? pull down m s 26 37 dspi_1 cs3 alt1 ? ? dspi_0 cs4 alt3 ? ? swg analog output ?? ? d[8] pcr[56] siul gpio[56] alt0 gpio[56] ? pull down m s 21 32 dspi_1 cs2 alt1 ? ? etimer_1 etc[4] alt2 etc[4] psmi[13]; padsel=2 dspi_0 cs5 alt3 ? ? flexpwm_0 ? ? fault[3] psmi[19]; padsel=1 d[9] pcr[57] siul gpio[57] alt0 gpio[57] ? pull down m s 15 26 flexpwm_0 x[0] alt1 x[0] ? linflexd_1 txd alt2 ? ? d[10] pcr[58] siul gpio[58] alt0 gpio[58] ? pull down m s 53 76 flexpwm_0 a[0] alt1 a[0] psmi[20]; padsel=1 etimer_0 ? ? etc[0] psmi[35]; padsel=1 d[11] pcr[59] siul gpio[59] alt0 gpio[59] ? pull down m s 54 78 flexpwm_0 b[0] alt1 b[0] psmi[24]; padsel=1 etimer_0 ? ? etc[1] psmi[36]; padsel=1 d[12] pcr[60] siul gpio[60] alt0 gpio[60] pull down m s 70 99 flexpwm_0 x[1] alt1 x[1] psmi[28]; padsel=1 linflexd_1 ? ? rxd psmi[32]; padsel=1 d[14] pcr[62] siul gpio[62] alt0 gpio[62] ? pull down m s 73 105 flexpwm_0 b[1] alt1 b[1] psmi[25]; padsel=2 etimer_0 ? ? etc[3] psmi[38]; padsel=1 table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg
docid023953 rev 4 67/126 spc56xl70lx package pinouts and signal descriptions 125 port e e[0] pcr[64] siul ? alt0 gpi[64] ? ???4668 adc_1 ? ? an[5] (3) ? e[2] pcr[66] siul ? alt0 gpi[66] ? ???3249 adc_0 ? ? an[5] (3) ? e[4] pcr[68] siul ? alt0 gpi[68] ? ????42 adc_0 ? ? an[7] (3) ? e[5] pcr[69] siul ? alt0 gpi[69] ? ????44 adc_0 ? ? an[8] (3) ? e[6] pcr[70] siul ? alt0 gpi[70] ? ????46 adc_0 ? ? an[4] (3) ? e[7] pcr[71] siul ? alt0 gpi[71] ? ????48 adc_0 ? ? an[6] (3) ? e[9] pcr[73] siul ? alt0 gpi[73] ? ????61 adc_1 ? ? an[7] (3) ? e[10] pcr[74] siul ? alt0 gpi[74] ? ????63 adc_1 ? ? an[8] (3) ? e[11] pcr[75] siul ? alt0 gpi[75] ? ????65 adc_1 ? ? an[4] (3) ? e[12] pcr[76] siul ? alt0 gpi[76] ? ????67 adc_1 ? ? an[6] (3) ? e[13] pcr[77] siul gpio[77] alt0 gpio[77] ? pull down ms?117 etimer_0 etc[5] alt1 etc[5] psmi[8]; padsel=1 dspi_2 cs3 alt2 ? ? siul ? ? eirq[25] ? e[14] pcr[78] siul gpio[78] alt0 gpio[78] ? pull down ms?119 etimer_1 etc[5] alt1 etc[5] psmi[14]; padsel=3 siul ? ? eirq[26] ? e[15] pcr[79] siul gpio[79] alt0 gpio[79] ? pull down ms?121 dspi_0 cs1 alt1 ? ? siul ? ? eirq[27] ? table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg
package pinouts and signal descriptions spc56xl70lx 68/126 docid023953 rev 4 port f f[0] pcr[80] siul gpio[80] alt0 gpio[80] ? pull down ms?133 flexpwm_0 a[1] alt1 a[1] psmi[21]; padsel=2 etimer_0 ? ? etc[2] psmi[37]; padsel=1 siul ? ? eirq[28] ? f[3] pcr[83] siul gpio[83] alt0 gpio[83] ? pull down ms?139 dspi_0 cs6 alt1 ? ? f[4] pcr[84] siul gpio[84] alt0 gpio[84] ? pull down fs?4 npc mdo[3] alt2 ? ? f[5] pcr[85] siul gpio[85] alt0 gpio[85] ? pull down fs?5 npc mdo[2] alt2 ? ? f[6] pcr[86] siul gpio[86] alt0 gpio[86] ? pull down fs?8 npc mdo[1] alt2 ? ? f[7] pcr[87] siul gpio[87] alt0 gpio[87] ? pull down fs?19 npc mcko alt2 ? ? f[8] pcr[88] siul gpio[88] alt0 gpio[88] ? pull down fs?20 npc mseo[1] alt2 ? ? f[9] pcr[89] siul gpio[89] alt0 gpio[89] ? pull down fs?23 npc mseo[0] alt2 ? ? f[10] pcr[90] siul gpio[90] alt0 gpio[90] ? pull down fs?24 npc evto alt2 ? ? f[11] pcr[91] siul gpio[91] alt0 gpio[91] ? pull down ms?25 npc evti alt2 ? ? f[12] pcr[92] siul gpio[92] alt0 gpio[92] ? pull down ms?106 etimer_1 etc[3] alt1 etc[3] psmi[12]; padsel=2 siul ? ? eirq[30] ? f[13] pcr[93] siul gpio[93] alt0 gpio[93] ? pull down ms?112 etimer_1 etc[4] alt1 etc[4] psmi[13]; padsel=3 siul ? ? eirq[31] ? table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg
docid023953 rev 4 69/126 spc56xl70lx package pinouts and signal descriptions 125 f[14] pcr[94] siul gpio[94] alt0 gpio[94] ? pull down ms?115 linflexd_1 txd alt1 ? ? flexcan_2 rxd alt2 ? ? f[15] pcr[95] siul gpio[95] alt0 gpio[95] ? pull down ms?113 linflexd_1 ? ? rxd psmi[32]; padsel=2 flexcan_2 txd alt2 ? ? fccu fccu _ f[0] ? fccu f[0] alt0 f[0] ? ? s s 27 38 fccu _ f[1] ? fccu f[1] alt0 f[1] ? ? s s 97 141 port g g[2] pcr[98] siul gpio[98] alt0 gpio[98] ? pull down ms?102 flexpwm_0 x[2] alt1 x[2] psmi[29]; padsel=1 dspi_1 cs1 alt2 ? ? g[3] pcr[99] siul gpio[99] alt0 gpio[99] ? pull down ms?104 flexpwm_0 a[2] alt1 a[2] psmi[22]; padsel=2 etimer_0 ? ? etc[4] psmi[7]; padsel=3 g[4] pcr[100] siul gpio[100] alt0 gpio[100] ? pull down ms?100 flexpwm_0 b[2] alt1 b[2] psmi[26]; padsel=2 etimer_0 ? ? etc[5] psmi[8]; padsel=3 g[5] pcr[101] siul gpio[101] alt0 gpio[101] ? pull down ms?85 flexpwm_0 x[3] alt1 x[3] psmi[30]; padsel=2 dspi_2 cs3 alt2 ? ? g[6] pcr[102] siul gpio[102] alt0 gpio[102] ? pull down ms?98 flexpwm_0 a[3] alt1 a[3] psmi[23]; padsel=3 table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg
package pinouts and signal descriptions spc56xl70lx 70/126 docid023953 rev 4 g[7] pcr[103] siul gpio[103] alt0 gpio[103] pull down ms?83 flexpwm_0 b[3] alt1 b[3] psmi[27]; padsel=3 g[8] pcr[104] siul gpio[104] alt0 gpio[104] ? pull down ms?81 flexray dbg0 alt1 ? ? dspi_0 cs1 alt2 ? ? flexpwm_0 ? ? fault[0] psmi[16]; padsel=2 siul ? ? eirq[21] ? g[9] pcr[105] siul gpio[105] alt0 gpio[105] ? pull down ms?79 flexray dbg1 alt1 ? ? dspi_1 cs1 alt2 ? ? flexpwm_0 ? ? fault[1] psmi[17]; padsel=2 siul ? ? eirq[29] ? g[10] pcr[106] siul gpio[106] alt0 gpio[106] ? pull down ms?77 flexray dbg2 alt1 ? ? dspi_2 cs3 alt2 ? ? flexpwm_0 ? ? fault[2] psmi[18]; padsel=1 g[11] pcr[107] siul gpio[107] alt0 gpio[107] ? pull down ms?75 flexray dbg3 alt1 ? ? flexpwm_0 ? ? fault[3] psmi[19]; padsel=2 g[12] pcr[108] siul gpio[108] alt0 gpio[108] ? pull down fs?? npc mdo[11] alt2 ? ? g[13] pcr[109] siul gpio[109] alt0 gpio[109] ? pull down fs?? npc mdo[10] alt2 ? ? g[14] pcr[110] siul gpio[110] alt0 gpio[110] ? pull down fs?? npc mdo[9] alt2 ? ? g[15] pcr[111] siul gpio[111] alt0 gpio[111] ? pull down fs?? npc mdo[8] alt2 ? ? table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg
docid023953 rev 4 71/126 spc56xl70lx package pinouts and signal descriptions 125 port h h[0] pcr[112] siul gpio[112] alt0 gpio[112] ? pull down fs?? npc mdo[7] alt2 ? ? h[1] pcr[113] siul gpio[113] alt0 gpio[113] ? pull down fs?? npc mdo[6] alt2 ? ? h[2] pcr[114] siul gpio[114] alt0 gpio[114] ? pull down fs?? npc mdo[5] alt2 ? ? h[3] pcr[115] siul gpio[115] alt0 gpio[115] ? pull down fs?? npc mdo[4] alt2 ? ? h[4] pcr[116] siul gpio[116] alt0 gpio[116] ? pull down ms?? flexpwm_1 x[0] alt1 x[0] ? etimer_2 etc[0] alt2 etc[0] psmi[39]; padsel=0 h[5] pcr[117] siul gpio[117] alt0 gpio[117] ? pull down ms?? flexpwm_1 a[0] alt1 a[0] ? dspi_0 cs4 alt3 ? ? h[6] pcr[118] siul gpio[118] alt0 gpio[118] ? pull down ms?? flexpwm_1 b[0] alt1 b[0] ? dspi_0 cs5 alt3 ? ? h[7] pcr[119] siul gpio[119] alt0 gpio[119] ? pull down ms?? flexpwm_1 x[1] alt1 x[1] ? etimer_2 etc[1] alt2 etc[1] psmi[40]; padsel=0 h[8] pcr[120] siul gpio[120] alt0 gpio[120] ? pull down ms?? flexpwm_1 a[1] alt1 a[1] ? dspi_0 cs6 alt3 ? ? h[9] pcr[121] siul gpio[121] alt0 gpio[121] ? pull down ms?? flexpwm_1 b[1] alt1 b[1] ? dspi_0 cs7 alt3 ? ? h[10] pcr[122] siul gpio[122] alt0 gpio[122] ? pull down ms?? flexpwm_1 x[2] alt1 x[2] ? etimer_2 etc[2] alt2 etc[2] ? table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg
package pinouts and signal descriptions spc56xl70lx 72/126 docid023953 rev 4 h[11] pcr[123] siul gpio[123] alt0 gpio[123] ? pull down ms?? flexpwm_1 a[2] alt1 a[2] ? h[12] pcr[124] siul gpio[124] alt0 gpio[124] ? pull down ms?? flexpwm_1 b[2] alt1 b[2] ? h[13] pcr[125] siul gpio[125] alt0 gpio[125] ? pull down ms?? flexpwm_1 x[3] alt1 x[3] ? etimer_2 etc[3] alt2 etc[3] psmi[42]; padsel=0 h[14] pcr[126] siul gpio[126] alt0 gpio[126] ? pull down ms?? flexpwm_1 a[3] alt1 a[3] ? etimer_2 etc[4] alt2 etc[4] ? h[15] pcr[127] siul gpio[127] alt0 gpio[127] ? pull down ms?? flexpwm_1 b[3] alt1 b[3] ? etimer_2 etc[5] alt2 etc[5] ? port i i[0] pcr[128] siul gpio[128] alt0 gpio[128] ? pull down ms?? etimer_2 etc[0] alt1 etc[0] psmi[39]; padsel=1 dspi_0 cs4 alt2 ? ? flexpwm_1 ? ? fault[0] ? i[1] pcr[129] siul gpio[129] alt0 gpio[129] ? pull down ms?? etimer_2 etc[1] alt1 etc[1] psmi[40]; padsel=1 dspi_0 cs5 alt2 ? ? flexpwm_1 ? ? fault[1] ? i[2] pcr[130] siul gpio[130] alt0 gpio[130] ? pull down ms?? etimer_2 etc[2] alt1 etc[2] psmi[41]; padsel=1 dspi_0 cs6 alt2 ? ? flexpwm_1 ? ? fault[2] ? table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg
docid023953 rev 4 73/126 spc56xl70lx package pinouts and signal descriptions 125 i[3] pcr[131] siul gpio[131] alt0 gpio[131] ? pull down ms?? etimer_2 etc[3] alt1 etc[3] psmi[42]; padsel=1 dspi_0 cs7 alt2 ? ? ctu_0 ext_tgr alt3 ? ? flexpwm_1 ? ? fault[3] ? rdy pcr[132] siul gpio[132] alt0 gpio[132] ? pull down fs?? npc rdy alt2 ? ? 1. programmable via the src (slew rate control) bit in the respective pad configuration register; s = slow, m = medium, f = fast, sym = symmetric (for flexray) 2. the default function of this pin out of reset is alt1 (tdo). 3. analog table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg
electrical characteristics spc56xl70lx 74/126 docid023953 rev 4 3 electrical characteristics 3.1 introduction this section contains detailed information on power considerations, dc/ac electrical characteristics, and ac timing specifications for this device. this device is designed to operate at 120 mhz. the electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. these specifications may not be fully tested or guaranteed at this early stage of the product life cycle. finalized specifications will be published after complete characterization and device qualifications have been completed. the ?symbol? column of the electrical parameter and timings tables contains an additional column containing ?sr?, ?cc?, ?p?, ?c?, ?t?, or ?d?. ? ?sr? identifies system requirements?conditions that must be provided to ensure normal device operation. an example is the input voltage of a voltage regulator. ? ?cc? identifies controller characteristics?indicating the characteristics and timing of the signals that the chip provides. ? ?p?, ?c?, ?t?, or ?d? apply only to controller characteristics?specifications that define normal device operation. they specify how each characteristic is guaranteed. ? p: parameter is guaranteed by production testing of each individual device. ? c: parameter is guaranteed by design characterization. measurements are taken from a statistically relevant sample size across process variations. ? t: parameter is guaranteed by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values are shown in the typical (?typ?) column are within this category. ? d: parameters are derived mainly from simulations. 3.2 absolute maximum ratings table 8. absolute maximum ratings (1) symbol parameter conditions min max unit v dd_hv_reg sr 3.3 v voltage regulator supply voltage ? ?0.3 4.5 (2), (3) v v dd_hv_iox sr 3.3 v input/output supply voltage ? ?0.3 4.5 (2), (3) v v ss_hv_iox sr input/output ground voltage ? ?0.1 0.1 v v dd_hv_fla sr 3.3 v flash supply voltage ? ?0.3 4.5 (2), (3) v v ss_hv_fla sr flash memory ground ? ?0.1 0.1 v v dd_hv_osc sr 3.3 v crystal oscillator amplifier supply voltage ??0.34.5 (2), (3) v v ss_hv_osc sr 3.3 v crystal oscillator amplifier reference voltage ??0.10.1v v dd_hv_adr0 (2), (3) v dd_hv_adr1 sr 3.3 v / 5.0 v adc_0 high reference voltage 3.3 v / 5.0 v adc_1 high reference voltage ??0.36.4 (2) v
docid023953 rev 4 75/126 spc56xl70lx electrical characteristics 125 3.3 recommended operating conditions v ss_hv_adr0 v ss_hv_adr1 sr adc_0 ground and low reference voltage adc_1 ground and low reference voltage ??0.10.1v v dd_hv_adv sr 3.3 v adc supply voltage ? ?0.3 4.5 (3), (4) v v ss_hv_adv sr 3.3 v adc supply ground ? ?0.1 0.1 v tv dd sr supply ramp rate ? 3.0 10 -6 (3.0 v/sec) 0.5 v/s v/s v in sr voltage on any pin with respect to ground (v ss_hv_io x )or v ss_hv_adrx valid only for adc pins ?0.3 6.0 (4) v relative to v dd ?0.3 v dd +0.3 (4), (5) i injpad sr injected input current on any pin during overload condition ? ?10 10 ma i injsum sr absolute sum of all injected input currents during overload condition ? ?50 50 ma t stg sr storage temperature ? ?55 150 c 1. functional operating conditions are given in the dc electrical characteristics. absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guarant eed. exposure to absolute maximum rating conditions for extended periods may affect device reliabilit y or cause permanent damage to the device. 2. any voltage between operating condition and absolute max rating can be sustained for maximum cumulative time of 10 hours. 3. voltage overshoots during a high-to-low or low-to-hig h transition must not exceed 10 seconds per instance. 4. internal structures hold the input voltage less than the ma ximum voltage on all pads powered by vdde supplies, if the maximum injection current specification is met (2 ma for all pins) and vdde is within the operating voltage specifications. 5. v dd has to be considered equal to to v dd_hv_adrx in case of adc pins, whilst it is v dd_hv_iox for any other pin. table 8. absolute maximum ratings (1) (continued) symbol parameter conditions min max unit table 9. recommended operating conditions (3.3 v) symbol parameter conditions min (1) max unit v dd_hv_reg sr 3.3 v voltage regulator supply voltage ? 3.0 3.63 v v ss_hv_reg sr 3.3 v voltage regulator reference voltage ? 0 0 v v dd_hv_iox sr 3.3 v input/output supply voltage ? 3.0 3.63 v v ss_hv_iox sr input/output ground voltage ? 0 0 v v dd_hv_fla sr 3.3 v flash supply voltage ? 3.0 3.6 v v ss_hv_fla sr flash memory ground ? 0 0 v v dd_hv_osc sr 3.3 v crystal oscillator amplifier supply voltage ?3.03.63v v ss_hv_osc sr 3.3 v crystal oscillator amplifier reference voltage ?00v v dd_hv_adr0 (2) , (3) v dd_hv_adr1 sr 3.3 v / 5.0 v adc_0 high reference voltage 3.3 v / 5.0 v adc_1 high reference voltage ? 4.5 to 5.5 or 3.0 to 3.63 v
electrical characteristics spc56xl70lx 76/126 docid023953 rev 4 3.4 thermal characteristics v dd_hv_adv sr 3.3 v adc supply voltage ? 3.0 3.63 v v ss_hv_ad0 v ss_hv_ad1 sr adc_0 ground and low reference voltage adc_1 ground and low reference voltage ?00v v ss_hv_adv sr 3.3 v adc supply ground ? 0 0 v v dd_lv_regcor (4) sr internal supply voltage ? ? ? v v ss_lv_regcor (5) sr internal reference voltage ? 0 0 v v dd_lv_cor x (2) sr internal supply voltage ? ? ? v v ss_lv_cor x (3) sr internal reference voltage ? 0 0 v v dd_lv_pll (2) sr internal supply voltage ? ? ? v v ss_lv_pll (3) sr internal reference voltage ? 0 0 v t a sr ambient temperature under bias f cpu 120 mhz ?40 125 c t j sr junction temperature under bias ? ?40 150 c 1. full functionality cannot be guaranteed when voltage drops below 3.0 v. in particular, adc electrical characteristics and i/os dc electrical specification may not be guaranteed. 2. v dd_hv_adr0 and v dd_hv_adr1 cannot be operated at different voltages, and need to be supplied by the same voltage source. 3. vdd_hv_adrx must always be applied and should be stable before lbist starts. if this supply is not above its absolute minimum level, lbist operations can fail. 4. can be connected to emitter of external npn. low voltage supplies are not under user cont rol. they are produced by an on-chip voltage regulator. 5. for the device to function properly, the low voltage grounds (v ss_lv_ xxx ) must be shorted to high voltage grounds (v ss_hv_ xxx ) and the low voltage supply pins (v dd_lv_ xxx ) must be connected to the external ballast emitter, if one is used. table 9. recommended operating conditions (3.3 v) (continued) symbol parameter conditions min (1) max unit table 10. thermal characteristics for lqfp100 package (1) symbol parameter conditions value unit r ja d thermal resistance, junction-to-ambient natural convection (2) single layer board ? 1s 46 c/w four layer board ? 2s2p 34 r jma d thermal resistance, junction-to-ambient forced convection at 200 ft/min single layer board ? 1s 36 c/w four layer board ? 2s2p 28 r jb d thermal resistance junction-to-board (3) ?19c/w r jc d thermal resistance junction-to-case (4) ?8c/w jt d junction-to-package-top natural convection (5) ?2c/w 1. junction temperature is a function of di e size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power diss ipation of other components on the board, and board thermal resistance. 2. junction-to-ambient thermal resistance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. 3. junction-to-board thermal resistance determined per jede c jesd51-8. thermal test board meets jedec specification for the specified package.
docid023953 rev 4 77/126 spc56xl70lx electrical characteristics 125 3.4.1 general notes for specifications at maximum junction temperature an estimation of the chip junction temperature, t j , can be obtained from equation 1 : equation 1 t j =t a +(r ja p d ) where: t a = ambient temperature for the package ( o c) r ja = junction to ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) the junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. for packages such as the pbga, these values can be different by a factor of two. which value is closer to the application depends on the power dissipated by other components on the board. the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. the value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. when a heat sink is used, the thermal resistance is expressed in equation 2 as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: 4. junction-to-case at the top of the package determined usi ng mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported value incl udes the thermal resistance of the interface layer. 5. thermal characterization parameter indicating the tem perature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the therma l characterization parameter is written as psi-jt. table 11. thermal characteristics for lqfp144 package (1) symbol parameter conditions value unit r ja d thermal resistance, junction-to-ambient natural convection (2) single layer board ? 1s 42 c/w four layer board ? 2s2p 34 r jma d thermal resistance, junction-to-ambient forced convection at 200 ft/min single layer board ? 1s 35 c/w four layer board ? 2s2p 30 r jb d thermal resistance junction-to-board (3) ?24c/w r jc d thermal resistance junction-to-case (4) ?8c/w jt d junction-to-package-top natural convection (5) ?2c/w 1. thermal characteristics are target s based on simulation that are subject to change per device characterization. 2. junction-to-ambient thermal resistance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. 3. junction-to-board thermal resistance determined per jede c jesd51-8. thermal test board meets jedec specification for the specified package. 4. junction-to-case at the top of the package determined usi ng mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported value incl udes the thermal resistance of the interface layer. 5. thermal characterization parameter indicating the tem perature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the therma l characterization parameter is written as psi-jt.
electrical characteristics spc56xl70lx 78/126 docid023953 rev 4 equation 2 r ja =r jc + r ca where: r ja = junction to ambient thermal resistance (c/w) r jc = junction to case thermal resistance (c/w) r ca = case to ambient thermal resistance (c/w) r jc is device related and cannot be influenced by the user. the user controls the thermal environment to change the case to ambient thermal resistance, r ca . for instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. to determine the junction temperature of the device in the application when heat sinks are not used, the thermal characterization parameter ( jt ) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using equation 3 : equation 3 t j =t t +( jt p d ) where: t t = thermocouple temperature on top of the package (c) jt = thermal characterization parameter (c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured per jesd51-2 specification using a 40 gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. references semiconductor equipment and materials international 3081 zanker road san jose, ca 95134 usa (408) 943-6900 mil-spec and eia/jesd (jedec) specifications are available from global engineering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org . 1. c.e. triplett and b. joiner, ?an experimental characterization of a 272 pbga within an automotive engine controller module,? proceedings of semitherm, san diego, 1998, pp. 47?54. 2. g. kromann, s. shidore, and s. addison, ?thermal modeling of a pbga for air-cooled applications,? electronic packaging and production, pp. 53?58, march 1998. 3. b. joiner and v. adams, ?measurement and simulation of junction to board thermal resistance and its application in thermal modeling,? proceedings of semitherm, san diego, 1999, pp. 212?220.
docid023953 rev 4 79/126 spc56xl70lx electrical characteristics 125 3.5 electromagnetic interference (emi) characteristics the characteristics in ta ble 13 were measured using: ? device configuration, tet conditions, and em testing per standard iec61967-2 ? supply voltage of 3.3 v dc ? ambient temperature of 25 c the configuration information referenced in ta ble 13 is explained in tab le 12 . eme testing was performed and documented according to these standards: [iec 61967-2 & -4] ems testing was performed and documented according to these standards: [iec 62132-2 & -4] table 12. emi configuration summary configuration name description configuration a ? high emission = all pads have max slew rate, lvds pads running at 40 mhz ? oscillator frequency = 40 mhz ? system bus frequency = 120 mhz ? no pll frequency modulation ? iec level k ( 30 db v) configuration b ? reference emission = pads use min, mid and max slew rates, lvds pads disabled ? oscillator frequency = 40 mhz ? system bus frequency = 120 mhz ? 2% pll frequency modulation ? iec level k( 30 db v) table 13. emi emission testing specifications symbol parameter conditions min typ max unit v eme cc radiated emissions configuration a; frequency range 150 khz?50 mhz ?10?db v configuration a; frequency range 50? 150 mhz ?18? configuration a; frequency range 150? 500 mhz ?30? configuration a; frequency range 500? 1000 mhz ?18? configuration b; frequency range 50? 150 mhz ?10? configuration b; frequency range 50? 150 mhz ?18? configuration b; frequency range 150? 500 mhz ?30? configuration b; frequency range 500? 1000 mhz ?18?
electrical characteristics spc56xl70lx 80/126 docid023953 rev 4 3.6 electrostatic discharge (esd) characteristics electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts ( n + 1) supply pin). this test conforms to the aec-q100-002/-003/-011 standard. for more details, refer to the application note electrostatic discharge sensitivity measurement (an1181). 3.7 static latch-up (lu) two complementary static tests are required on six parts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin. ? a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with the eia/jesd 78 ic latch-up standard. table 14. esd ratings (1)(2) no. symbol parameter conditions class max value (3) unit 1v esd(hbm) sr electrostatic discharge (human body model) t a =25c conforming to aec-q100- 002 h1c 2000 v 2v esd(mm) sr electrostatic discharge (machine model) t a =25c conforming to aec-q100- 003 m2 200 v 3v esd(cdm) sr electrostatic discharge (charged device model) t a =25c conforming to aec-q100- 011 c3a 500 v 750 (corners) 1. all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. 2. a device will be defined as a failure if after exposure to esd pulses the device no longer m eets the device specification requirements. complete dc parametric and functional test ing shall be performed per applic able device specification at room temperature followed by hot temperature, unless specified other wise in the device specification. 3. data based on characterization results, not tested in production. table 15. latch-up results no. symbol parameter conditions class 1 lu sr static latch-up class t a = 125 c conforming to jesd 78 ii level a
docid023953 rev 4 81/126 spc56xl70lx electrical characteristics 125 3.8 voltage regulator electrical characteristics the voltage regulator is composed of the following blocks: ? high power regulator hpreg1 (internal ballast to support core current) ? high power regulator hpreg2 (external npn to support core current) ? low voltage detector (lvd_main_1) for 3.3 v supply to io (v ddio ) ? low voltage detector (lvd_main_2) for 3.3 v supply (v ddreg ) ? low voltage detector (lvd_main_3) for 3.3 v flash supply (v ddflash ) ? low voltage detector (lvd_dig_main) for 1.2 v digital core supply (hpv dd ) ? low voltage detector (lvd_dig_bkup) for the self-test of lvd_dig_main ? high voltage detector (hvd_dig_main) for 1.2 v digital core supply (hpv dd ) ? high voltage detector (hvd_dig_bkup) for the self-test of hvd_dig_main. ? power on reset (por) hpreg1 uses an internal ballast to support the core current. hpreg2 is used only when external npn transistor is present on board to supply core current. the spc56xl70 always powers up using hpreg1 if an external npn transistor is present. then the spc56xl70 makes a transition from hpreg1 to hpreg2. this transition is dynamic. once hpreg2 is fully operational, the controller part of hpreg1 is switched off. the following bipolar transistors are supported: ? bcp68 from on semiconductor ? bcx68 from infineon table 16. recommended operating characteristics symbol parameter value unit h fe ( ) dc current gain (beta) 85 - 375 ? p d maximum power dissipation @ t a =25c (1) 1.5 w i cmaxdc maximum peak collector current 1.0 a vce sat collector-to-emitter saturation voltage(max) 600 (2) mv v be base-to-emitter voltage (max) 1.0 v 1. derating factor 12mw/degc 2. adjust resistor at bipolar transistor collector for 3.3v to avoid vce electrical characteristics spc56xl70lx 82/126 docid023953 rev 4 table 17. voltage regulator electrical specifications symbol parameter conditions min typ max unit c ext external decoupling/ stability capacitor min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. 12 ? 40 f sr combined esr of external capacitor ? 1 ? 100 m sr number of pins for external decoupling/ stability capacitor ?5??? c v1v2 sr total capacitance on 1.2 v pins ceramic capacitors, taking into account tolerance, aging, voltage and temperature variation 300 ? 900 nf t su start-up time after main supply stabilization c load =10f4 ? ? 2.5 ms ? main high voltage power - low voltage detection, upper threshold ???2.93v ? d main supply low voltage detector, lower threshold ?2.6??v ? d digital supply high voltage detector upper threshold before a destructive reset initialization phase completion 1.355 ? 1.495 v after a destructive reset initialization phase completion 1.39 ? 1.47 ? d digital supply high voltage detector lower threshold before a destructive reset initialization phase completion 1.315 ? 1.455 v after a destructive reset initialization phase completion 1.35 ? 1.38 ? d digital supply low voltage detector lower threshold before a destructive reset initialization phase completion 1.080 ? 1.226 v ? d digital supply low voltage detector lower threshold after a destructive reset initialization phase completion 1.080 ? 1.140 v ? d digital supply low voltage detector upper threshold after a destructive reset initialization phase completion 1.16 ? 1.22 v
docid023953 rev 4 83/126 spc56xl70lx electrical characteristics 125 figure 4. bcp68 board schematic example note: the combined esr of the capacitors used on 1.2 v pins (v1v2 in the picture) shall be in the range of 1 m to 100 m . the minimum value of the esr is constrained by the resonance ? d digital supply low voltage detector upper threshold before a destructive reset initialization phase completion 1.16 ? 1.306 v ? d por rising/ falling supply threshold voltage ? 1.6 ? 2.6 v ? sr supply ramp rate ? 3 ? 0.5 10 6 v/s ? d lvd_main: time constant of rc filter at lvd input 3.3v noise rejection at the input of lvd comparator 1.1 ? ? s ? d hvd_dig: time constant of rc filter at lvd input 1.2v noise rejection at the input of lvd comparator 0.1 ? ? s ? d lvd_dig: time constant of rc filter at lvd input 1.2v noise rejection at the input of lvd comparator 0.1 ? ? s table 17. voltage regulator electrical specifications (continued) symbol parameter conditions min typ max unit bcrtl c ext c int r b l b r s v1v2 ring on board v dd v1v2 pin esr c v1v2 spc56xl70 bcp68
electrical characteristics spc56xl70lx 84/126 docid023953 rev 4 caused by the external components, bonding inductance, and internal decoupling. the minimum esr is required to avoid the resonance and make the regulator stable. dc electrical characteristics ta ble 18 gives the dc electrical characteristics at 3.3 v (3.0 v < v dd_hv_io x <3.6v). table 18. dc electrical characteristics (1) symbol parameter conditions min typ max unit v il d minimum low level input voltage ? ?0.1 (2) ??v v il p maximum level input voltage ? ? ? 0.35 v dd_hv_iox v v ih p minimum high level input voltage ? 0.65 v dd_hv_iox ??v v ih d maximum high level input voltage ? ? ? v dd_hv_iox +0.1 (2) , (3) v v hys t schmitt trigger hysteresis ? 0.1 v dd_hv_io x ??v v ol_s p slow, low level output voltage i ol =1.5ma ? ? 0.5 v v oh_s p slow, high level output voltage i oh = ? 1.5 ma v dd_hv_io x ? 0.8 ??v v ol_m p medium, low level output voltage i ol =2ma ? ? 0.5 v v oh_m p medium, high level output voltage i oh =?2ma v dd_hv_iox ? 0.8 ??v v ol_f p fast, high level output voltage i ol =11ma ? ? 0.5 v v oh_f p fast, high level output voltage i oh =?11ma v dd_hv_io x ? 0.8 ??v v ol_sym p symmetric, high level output voltage i ol =1.5ma ? ? 0.5 v v oh_sym p symmetric, high level output voltage i oh =? 1.5 ma v dd_hv_io x ? 0.8 ??v i inj t dc injection current per pin (all bi- directional ports) ??1?1ma i pu p equivalent pull-up current v in =v il ?130 ? ? a v in =v ih ?? ?10 i pd p equivalent pull-down current v in =v il 10 ? ? a v in =v ih ?? 130 i il p input leakage current (all bidirectional ports) t j = ?40 to +150 c ?1 ? 1 a input leakage current (all adc input-only ports) ?0.25 ? 0.25 input leakage current (shared adc input-only ports) ?0.3 ? 0.3 v ilr p reset , low level input voltage ? ?0.1 (2) ?0.35v dd_hv_io x v v ihr p reset , high level input voltage ? 0.65 v dd_hv_io x ?v dd_hv_iox +0.1 (2) v v hysr d reset , schmitt trigger hysteresis ? 0.1 v dd_hv_io x ??v v olr d reset , low level output voltage i ol =2ma ? ? 0.5 v
docid023953 rev 4 85/126 spc56xl70lx electrical characteristics 125 3.9 supply current characteristics current consumption data is given in ta ble 19 . these specifications are design targets and are subject to change per device characterization. i pd d reset , equivalent pull-down current v in =v il 10 ? ? a v in =v ih ?? 130 1. these specifications are design targets and subject to change per dev ice characterization. 2. ?sr? parameter values must not exceed the absolute maximum ratings shown in ta b le 8 . 3. the max input voltage on the adc pins is the adc reference voltage vdd_hv_adrx. table 18. dc electrical characteristics (1) (continued) symbol parameter conditions min typ max unit table 19. current consumption characteristics symbol parameter conditions (1) min typ max unit i dd_lv_full +i dd_lv_pll t operating current 1.2 v supplies t j = ambient v dd_lv_cor =1.32v ? ? 25 [ma]+2.7 [ma/mhz] *f cpu [mhz] ma 1.2 v supplies t j =150 c v dd_lv_cor =1.32v ? ? 115 [ma]+2.28 [ma/m hz]*f cpu [mhz] i dd_lv_typ +i dd_lv_pll (2) t operating current 1.2 v supplies t j = ambient v dd_lv_cor =1.32v ? ? 25 [ma]+2.45 [ma/mh z]*f cpu [mhz] ma 1.2 v supplies t j =150 c v dd_lv_cor =1.32v ? ? 115 [ma]+2.02 [ma/m hz]*f cpu [mhz] i dd_lv_typ +i dd_lv_pll (2) p operating current 1.2 v supplies t j = ambient v dd_lv_cor =1.32v ?? 319 ma 1.2 v supplies t j =150 c v dd_lv_cor =1.32v ?? 358 i dd_lv_bist +i dd_lv_pll t operating current 1.2 v supplies during lbist (full lbist configuration) t j = ambient v dd_lv_cor =1.32v ?? 286 ma 1.2 v supplies during lbist (full lbist configuration) t j =150 c v dd_lv_cor =1.32v ?? 326 i dd_lv_typ + i dd_lv_pll t operating current 1.2 v supplies tj = 105 c v dd_lv_cor = 1.2 v ?? 315 ma
electrical characteristics spc56xl70lx 86/126 docid023953 rev 4 i dd_lv_typ + i dd_lv_pll t operating current 1.2 v supplies tj = 125 c v dd_lv_cor = 1.2 v ?? 339 ma i dd_lv_typ + i dd_lv_pll t operating current 1.2 v supplies tj = 105 c v dd_lv_cor = 1.2 v dpm mode ?? 193 ma i dd_lv_typ + i dd_lv_pll t operating current 1.2 v supplies tj = 125 c v dd_lv_cor = 1.2 v dpm mode ?? 231 ma i dd_lv_typ + i dd_lv_pll t operating current 1.2 v supplies tj = 150 c v dd_lv_cor = 1.2 v dpm mode ?? 277 ma i dd_lv_stop t operating current in v dd stop mode t j =25 c v dd_lv_cor =1.32v ?? 25 ma tt j =55 c v dd_lv_cor =1.32v ?? 53 pt j =150 c v dd_lv_cor =1.32v ?? 115 i dd_lv_halt t operating current in v dd halt mode t j =25 c v dd_lv_cor =1.32v ?? 30 ma tt j =55 c v dd_lv_cor =1.32v ?? 71 pt j =150 c v dd_lv_cor =1.32v ?? 125 i dd_hv_adc (3),(4) t operating current t j =150 c 120 mhz adc operating at 60 mhz v dd_hv_adc =3.6v ?? 11 ma i dd_hv_aref (4) t operating current t j =150 c 120 mhz adc operating at 60 mhz v dd_hv_ref =3.6v ?? 4 ma t j =150 c 120 mhz adc operating at 60 mhz v dd_hv_ref =5.5v ?? 6 i dd_hv_osc (oscillator bypass mode) t operating current t j =150 c 3.3 v supplies 120 mhz ?? 900 a table 19. current consumption characteristics (continued) symbol parameter conditions (1) min typ max unit
docid023953 rev 4 87/126 spc56xl70lx electrical characteristics 125 3.10 temperature sensor electrical characteristics 3.11 main oscillator electrical characteristics the device provides an oscillator/resonator driver. figure 5 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator. i dd_hv_osc (crystal oscillator mode) d operating current t j =150 c 3.3 v supplies 120 mhz ?? 3.5 ma i dd_hv_flash (5) t operating current t j =150 c 3.3 v supplies 120 mhz ?? 4 ma i dd_hv_pmu t operating current t j =150 c 3.3 v supplies 120 mhz ?? 10 ma 1. devices configured for dpm mode, single core only with core 0 executing typical code at 120 mhz from sram and core 1 in reset. if core execution mode not specified, the device is configured for lsm mode with both cores executing typical code at 120 mhz from sram. 2. enabled modules in 'typical mode': flexpwm0, etimer0/1/2, ctu, swg, dma, flexcan0/1, linflex, adc1, dspi0/1, pit, crc, pll0/1, i/o supply current excluded 3. internal structures hold the input voltage less than vdda + 1.0 v on all pads powered by vdda supplies, if the maximum injection current specification is met and vdda is within the operating voltage specifications. 4. this value is the total current for both adcs. 5. vflash is only available in the calibration package. table 19. current consumption characteristics (continued) symbol parameter conditions (1) min typ max unit table 20. temperature sensor electrical characteristics symbol parameter conditions min max unit ? p accuracy t j = ?40 c to 150 c ?10 10 c t s d minimum sampling period ? 4 ? s
electrical characteristics spc56xl70lx 88/126 docid023953 rev 4 figure 5. crystal oscillator and resonator connection scheme note: xtal/extal must not be directly used to drive external circuits. figure 6. main oscillator electrical characteristics c l c l crystal xtal extal r p resonator xtal extal device device device xtal extal i r v dd v xoschsop t xoschssu v xtal v xoschs valid internal clock 90% 10% 1/f xoschs mtrans 1 0 table 21. main oscillator electrical characteristics symbol parameter conditions (1) value unit min typ max f xoschs sr oscillator frequency ? 4.0 ? 40.0 mhz g mxoschs p oscillator transconductance v dd = 3.3 v 10% 4.5 ? 13.25 ma/v
docid023953 rev 4 89/126 spc56xl70lx electrical characteristics 125 3.12 fmpll electrical characteristics v xoschs d oscillation amplitude f osc = 4, 8, 10, 12, 16 mhz 1.3 ? ? v f osc =40mhz 1.1 ? ? v xoschsop d oscillation operating point ??0.82?v i xoschs d oscillator consumption ? ? ? 3.5 ma t xoschssu t oscillator start-up time f osc = 4, 8, 10, 12 mhz (2) ?? 6 ms f osc = 16, 40 mhz (2) ?? 2 v ih sr input high level cmos schmitt trigger oscillator bypass mode 0.65 v dd ?v dd +0.4 v v il sr input low level cmos schmitt trigger oscillator bypass mode ?0.4 ? 0.35 v dd v 1. v dd = 3.3 v 10%, t j = ?40 to +150 c, unless otherwise specified. 2. the recommended configuration for maximizing the oscillator margin are: xosc_margin = 0 for 4 mhz quartz xosc_margin = 1 for 8/16/40 mhz quartz table 21. main oscillator electrical characteristics (continued) symbol parameter conditions (1) value unit min typ max table 22. fmpll electrical characteristics symbol parameter conditions min typ max unit f ref_crystal f ref_ext d fmpll reference frequency range (1) crystal reference 4 ? 40 mhz f pll_in d phase detector input frequency range (after pre- divider) ?4?16mhz f fmpllout d clock frequency range in normal mode ? 4 ? 120 (2) mhz f free p free running frequency measured using clock division (typically 16) 20 ? 150 mhz f sys don-chip fmpll frequency (2) ?16?120mhz t cyc d system clock period ? ? ? 1 / f sys ns f lorl f lorh d loss of reference frequency window (3) lower limit 1.6 ? 3.7 mhz upper limit 24 ? 56 f scm d self-clocked mode frequency (4),(5) ?20?150mhz t lock p lock time stable oscillator (f pllin =4mhz), stable v dd ??200 s
electrical characteristics spc56xl70lx 90/126 docid023953 rev 4 t lpll d fmpll lock time (6), (7) ???200 s t dc d duty cycle of reference ?40?60% c jitter t clkout period jitter (8),(9),(10),(11) long-term jitter (avg. over 2 ms interval), f fmpllout maximum ?6 ? 6 ns t pkjit t single period jitter (peak to peak) phi @ 120 mhz, input clock @ 4 mhz ??175 ps phi @ 100 mhz, input clock @ 4 mhz ??185 ps phi @ 80 mhz, input clock @ 4 mhz ??200 ps t ltjit t long term jitter phi @ 16 mhz, input clock @ 4 mhz ??6 ns f lck d frequency lock range ? ?6 ? 6 % f fmpllout f ul d frequency un-lock range ? ?18 ? 18 % f fmpllout f cs f ds d modulation depth center spread 0.25 ? 2.0 % f fmpllout down spread ?0.5 ? -8.0 f mod d modulation frequency (12) ? ? ? 100 khz 1. considering operation with fmpll not bypassed. 2. with fm; the value does not include a possible +2% modulation 3. ?loss of reference frequency? window is the reference fr equency range outside of which the fmpll is in self clocked mode. 4. self clocked mode frequency is the frequency that the fmp ll operates at when the reference frequency falls outside the f lor window. 5. f vco is the frequency at the output of the vco; its range is 256?512 mhz. f scm is the self-clocked mode frequency (free running frequency); its range is 20?150 mhz. f sys =f vco odf 6. this value is determined by the crystal manufacturer and board design. for 4 mhz to 20 mhz crystals specified for this fmpll, load capacitors should not exceed these limits. 7. this specification applies to the period required for the fmpll to relock after changing the mfd frequency control bits in the synthesizer control register (syncr). 8. this value is determined by the crystal manufacturer and board design. 9. jitter is the average deviation from the programmed frequency meas ured over the specified interval at maximum f sys . measurements are made with the device powered by filtered s upplies and clocked by a stable external clock signal. noise injected into the fmpll circuitry via v ddpll and v sspll and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. 10. proper pc board layout procedures must be followed to achieve specifications. 11. values are with frequency modulation disabled. if fr equency modulation is enabled, jitter is the sum of c jitter and either f cs or f ds (depending on whether center spread or down spread modulation is enabled). 12. modulation depth is attenuated from depth setting when operating at modulation frequencies above 50 khz. table 22. fmpll electrical characteristics (continued) symbol parameter conditions min typ max unit
docid023953 rev 4 91/126 spc56xl70lx electrical characteristics 125 3.13 16 mhz rc oscillator electrical characteristics 3.14 adc electrical characteristics the device provides a 12-bit successive approximation register (sar) analog-to-digital converter. figure 7. adc characteristics and error definitions 3.14.1 input impedance and adc accuracy to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. this capacitor contributes to attenuating the noise present on the input pin; further, it table 23. rc oscillator electrical characteristics symbol parameter conditions min typical max unit f rc p rc oscillator frequency ta = 25 c ? 16 ? mhz rcmvar p fast internal rc oscillator variation over temperature and supply with respect to f rc at t a = 25 c in high- frequency configuration ??6?6% (2 ) (1) (3) (4) (5) offset error ose offset error ose gain error ge 1 lsb (ideal) v in(a) (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve code out 4095 4094 4093 4092 4091 4090 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 4089 4090 4091 4092 4093 4094 4095 1 lsb ideal =(vrefh-vrefl)/ 4096 = 3.3v/ 4096 = 0.806 mv total unadjusted error tue = +/- 6 lsb = +/- 4.84mv
electrical characteristics spc56xl70lx 92/126 docid023953 rev 4 sources charge during the sampling phase, when the analog signal source is a high- impedance source. a real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple rc filter). the rc filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. the filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the adc itself. in fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: c s being substantially a switched capacitance, with a frequency equal to the conversion rate of the adc, it can be seen as a resistive path to ground. for instance, assuming a conversion rate of 1 mhz, with c s equal to 3 pf, a resistance of 330 k is obtained (r eq =1 / (fs c p2 + c s ), where fs represents the conversion rate at the considered channel). to minimize the error induced by the voltage partitioning between this resistance (sampled voltage on c s ) and the sum of r s +r f +r l +r sw +r ad , the external circuit must be designed to respect the equation 4 : equation 4 equation 4 generates a constraint for external network design, in particular on resistive path. internal switch resistances (r sw and r ad ) can be neglected with respect to external resistances. figure 8. input equivalent circuit a second aspect involving the capacitance network shall be considered. assuming the three capacitances c f , c p1 and c p2 are initially charged at the source voltage v a (refer to the v a r s r f + r eq --------------------- ? 1 2 -- -lsb < r f c f r s r l r sw1 c p2 v dd sampling source filter current limiter external circuit internal circuit scheme rs source impedance rf filter resistance cf filter capacitance rl current limiter resistance rsw1 channel selection switch impedance radsampling switch impedance cp pin capacitance (two contributions, cp1 and cp2) cs sampling capacitance c p1 r ad channel selection v a
docid023953 rev 4 93/126 spc56xl70lx electrical characteristics 125 equivalent circuit reported in figure 8 ): a charge sharing phenomenon is installed when the sampling phase is started (a/d switch close). figure 9. transient behavior during sampling phase in particular two different transient periods can be distinguished: a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is equation 5 equation 5 can again be simplified considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: equation 6 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 7 : equation 7 a second charge transfer involves also c f (that is typically bigger than the on-chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality would be faster), the time constant is: v a v a1 v a2 t t s v cs voltage transient on c s v < 0.5 lsb 1 2 1 < (r sw + r ad ) c s << t s 2 = r l (c s + c p1 + c p2 ) 1 r sw r ad + () = c p c s ? c p c s + --------------------- ? 1 r sw r ad + () < c s t s ? ? v a1 c s c p1 c p2 ++ () ? v a c p1 c p2 + () ? =
electrical characteristics spc56xl70lx 94/126 docid023953 rev 4 equation 8 in this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t s , a constraints on r l sizing is obtained: equation 9 of course, r l shall be sized also according to the current limitation constraints, in combination with r s (source impedance) and r f (filter resistance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer transient) will be much higher than v a1 . equation 10 must be respected (charge balance assuming now c s already charged at v a1 ): equation 10 the two transients above are not influenced by the voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to compensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is typically designed to act as anti-aliasing. figure 10. spectral representation of input signal calling f 0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the 2 r l < c s c p1 c p2 ++ () ? 10 2 ? 10 r l c s c p1 c p2 ++ () ? ? =t s < v a2 c s c p1 c p2 c f +++ () ? v a c f ? v a1 +c p1 c p2 +c s + () ? = f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 f c (nyquist) f f = f 0 (anti-aliasing filtering condition) t c 2 r f c f (conversion rate vs. filter pole) noise
docid023953 rev 4 95/126 spc56xl70lx electrical characteristics 125 sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on c s ; from the two charge balance equations above, it is simple to derive equation 11 between the ideal and real sampled voltage on c s : equation 11 from this formula, in the worst case (when v a is maximum, that is for instance 5 v), assuming to accept a maximum error of half a count, a constraint is evident on c f value: equation 12 v a2 v a ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - = c f 8192 c s ? > table 24. adc conversion characteristics symbol parameter conditions (1) min typ max unit f ck s r adc clock frequency (depends on adc configuration) (the duty cycle depends on ad_ck (2) frequency) ?3?60mhz f s s r sampling frequency ? ? ? 983.6 (3) khz t sample d sample time (4) 60 mhz 383 ? ? ns t eval d evaluation time (5) 60 mhz 625 ? ? ns c s (6) d adc input sampling capacitance ? ? ? 7.32 pf c p1 (6) d adc input pin capacitance 1 ? ? ? 5 (7) pf c p2 (6) d adc input pin capacitance 2 ? ? ? 0.8 pf r sw1 (6) d internal resistance of analog source v ref range=4.5to5.5v ? ? 0.3 k v ref range = 3.0 to 3.6 v ? ? 875 w r ad (6) d internal resistance of analog source ? ? ? 825 w inl p integral non linearity ? ?3 ? 3 lsb dnl p differential non linearity (8) ??1?2lsb ofs t offset error ? ?6 ? 6 lsb gne t gain error ? ?6 ? 6 lsb is1winj ? (single adc channel) c max positive/negative injection ?3 ? 3 ma is1wwinj (double adc channel) c max positive/negative injection |vref_ad0 - vref_ad1| < 150mv ?3.6 ? 3.6 ma
electrical characteristics spc56xl70lx 96/126 docid023953 rev 4 3.15 flash memory electrical characteristics snr t signal-to-noise ratio vref = 3.3v 67 ? ? db snr t signal-to-noise ratio vref = 5.0v 69 ? ? db thd t total harmonic distortion ? -65 ? ? db sinad t signal-to-noise and distortion ? 65 ? ? db enob t effective number of bits ? 10.5 ? ? bits tue is1winj t total unadjusted error for is1winj (single adc channels) without current injection ?6 ? 6 lsb with current injection ?8 ? 8 lsb tue is1wwinj p total unadjusted error for is1wwinj (double adc channels) without current injection ?8 ? 8 lsb t with current injection ?10 ? 10 lsb 1. t j = ?40 to +150 c, unless otherwise specified and analog input voltage from v agnd to v aref. 2. ad_ck clock is always half of the adc module input clock defined via the auxiliary clock divider for the adc. 3. this is the maximum frequency that the analog portion of the adc can attain. a sustained conversion at this frequency is not possible. 4. during the sample time the input capacitance cs can be charged/discharged by the exte rnal source. the internal resistance of the analog source must allow the c apacitance to reach its final voltage level within t sample . after the end of the sample time t sample , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t sample depend on programming. 5. this parameter does not include the sample time t sample , but only the time for determining the digital result. 6. see figure 8 . 7. for the 144-pin package 8. no missing codes table 24. adc conversion characteristics (continued) symbol parameter conditions (1) min typ max unit table 25. flash memory program and erase electrical specifications no. symbol parameter typ (1) initial max (2) lifetime max (3) unit 1t dwprogram * (4) double word (64 bits) program time (4) 38 ? 500 s 2t pprogram * (4) page(128 bits) program time (4) 45 160 500 s 3t 16kpperase * (4) 16 kb block pre-program and erase time 270 1000 5000 ms 4t 48kpperase * (4) 48 kb block pre-program and erase time 625 1500 5000 ms 5t 64kpperase * (4) 64 kb block pre-program and erase time 800 1800 5000 ms 6t 128kpperase * (4) 128 kb block pre-program and erase time 1500 2600 7500 ms 7t 256kpperase * (4) 256 kb block pre-program and erase time 3000 5200 15000 ms 1. typical pr(4)ogram and erase times represent the medi an performance and assume nominal supply values and operation at 25 0 c. these values are characterized, but not tested.i 2. initial max program and erase times provide guidance for time-out limits used in the factory and apply for < 100 program/erase cycles, nominal supply values and operation at 25c. these values are verified at production test. 3. lifetime max program and erase times apply across the vo ltage, temperature, and cycling range of product life. these values are characterized, but not tested. 4. program times are actual hardware progr amming times and do not include software overhead.
docid023953 rev 4 97/126 spc56xl70lx electrical characteristics 125 table 26. flash memory timing symbol parameter value unit min typ max t res d time from clearing the mcr-esus or psus bit with ehv = 1 until done goes low ??100ns t done d time from 0 to 1 transition on the mcr-ehv bit initiating a program/erase until the mcr-done bit is cleared ?? 5ns t psrt d time between program suspend resume and the next program suspend request (1) 100 ? ? s t esrt d time between erase suspend resume and the next erase suspend request (2) 10 ? ? ms 1. repeated suspends at a high frequency may result in the operation timing out, and the flash module will respond by completing the operation with a fail code (mcr[peg] = 0), or the operation not able to finish (mcr[done] = 1 during program operation). the minimum time between su spends to ensure this does not occur is t psrt . 2. if erase suspend rate is less than t esrt , an increase of slope voltage ramp occurs during erase pulse. th is improves erase time but reduces cycling figure due to overstress table 27. flash memory module life no. symbol parameter value unit min typ max 1p/ec number of program/erase cycles per block for 16 kb, 48 kb, and 64 kb blocks over the operating temperature range (1) 100000 ? ? cycles 2p/ec number of program/erase cycles per block for 128 kb and 256 kb blocks over the operating temperature range (1) 1000 100000 (2) ?cycles 3 retention c minimum data retention at 85 c average ambient temperature (3) blocks with 0?1,000 p/e cycles blocks with 1,001?10,000 p/e cycles blocks with 10,001?100,000 p/e cycles 20 10 5 ? ? ? ? ? ? years 1. operating temperature range is t j from ?40 c to 150 c. typical endurance is evaluated at 25 c. 2. typical p/e cycles is 100,000 cycles for 128 kb and 256 kb blocks. 3. ambient temperature averaged over dur ation of application, not to exceed product operating temperature range.
electrical characteristics spc56xl70lx 98/126 docid023953 rev 4 3.16 swg electrical characteristics 3.17 ac specifications 3.17.1 pad ac specifications table 28. spc56xl70 swg specifications symbol parameter value minimum typical maximum t input clock 12 mhz 16 mhz 20 mhz t frequency range 1khz ? 50 khz t peak to peak (1) 1. peak to peak value is measured with no r or i load. 0.4 v ? 2.0v t peak to peak variation (2) 2. peak to peak excludes noise, sinad must be considered. -6% ? 6% t common mode (3) 3. common mode value is measured with no r or i load. ?1.3 v? t common mode variation -6% ? 6% tsinad (4) 4. sinad is measured at max peak to peak voltage. 45 db ? ? t load c 25 pf ? 100 pf t load i 0 a ? 100 a t esd pad resistance (5) 5. internal device routing resistance. esd pad resistance is in series and must be considered for max peak to peak voltages, depending on application i load and/or r load. 230 ?360 table 29. pad ac specifications (3.3 v , ipp_hve = 0) (1) no pad tswitchon 1 (ns) rise/fall (2) (ns) frequency (mhz) current slew (3) (ma/ns) load drive (pf) min typ max min typ max min typ max min typ max 1slowt 3?40??40?? 40.01? 2 25 3?40??50?? 20.01? 2 50 3 ? 40 ? ? 75 ? ? 2 0.01 ? 2 100 3 ? 40 ? ? 100 ? ? 2 0.01 ? 2 200 2mediumt 1 ? 15 ? ? 12 ? ? 40 2.5 ? 7 25 1 ? 15 ? ? 25 ? ? 20 2.5 ? 7 50 1 ? 15 ? ? 40 ? ? 13 2.5 ? 7 100 1 ? 15 ? ? 70 ? ? 7 2.5 ? 7 200
docid023953 rev 4 99/126 spc56xl70lx electrical characteristics 125 figure 11. pad output delay 3.18 reset sequence this section shows the duration for different reset sequences. it describes the different reset sequences and it specifies the start conditions and the end indication for the reset sequences. 3.18.1 reset sequence duration ta ble 30 specifies the minimum and the maximum reset sequence duration for the five different reset sequences described in section 3.18.2: reset sequence description . 3fastt 1 ? 6 ? ? 4 ? ? 72 3 ? 40 25 1 ? 6 ? ? 7 ? ? 55 7 ? 40 50 1 ? 6 ??12??40 7 ?40 100 1 ? 6 ??18??25 7 ?40 200 4symmetrict1? 8 ?? 5 ??50 3 ?25 25 1. propagation delay from v dd_hv_io x /2 of internal signal to pchannel/nchannel switch-on condition. 2. slope at rising/falling edge. 3. data based on characterization results, not tested in production. table 29. pad ac specifications (3.3 v , ipp_hve = 0) (1) (continued) no pad tswitchon 1 (ns) rise/fall (2) (ns) frequency (mhz) current slew (3) (ma/ns) load drive (pf) min typ max min typ max min typ max min typ max v dde /2 v oh v ol rising edge output delay falling edge output delay pad data input pad output
electrical characteristics spc56xl70lx 100/126 docid023953 rev 4 3.18.2 reset sequence description the figures in this section show the internal states of the chip during the five different reset sequences. the doted lines in the figures indicate the starting point and the end point for which the duration is specified in table 30 . the start point and end point conditions as well as the reset trigger mapping to the different reset sequences is specified in section 3.18.3: reset sequence trigger mapping . with the beginning of drun mode the first instruction is fetched and executed. at this point application execution starts and the internal reset sequence is finished. the figures below show the internal states of the chip during the execution of the reset sequence and the possible states of the signal pin reset . note: reset is a bidirectional pin. the voltage level on this pin can either be driven low by an external reset generator or by the chip internal reset circuitry. a high level on this pin can only be generated by an external pull up resistor which is strong enough to overdrive the weak internal pull down resistor. the rising edge on reset in the following figures indicates the time when the device stops driving it low. the reset sequence durations given in table ta ble 30 are applicable only if the internal reset sequence is not prolonged by an external reset generator keeping reset asserted low beyond the last phase3. figure 12. destructive reset sequence, bist enabled table 30. reset sequences no. symbol parameter conditions t reset unit min typ max (1) 1t drb cc destructive reset sequence, bist enabled 40 47 51 ms 2t dr cc destructive reset sequence, bist disabled ? 500 4200 5000 s 3t erlb cc external reset sequence long, bist enabled 41 45 49 ms 4t frl cc functional reset sequence long ? 35 150 400 s 5t frs cc functional reset sequence short ? 1 4 10 s 1. the maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of reset by an external reset generator. phase3 bist phase1,2 phase0 phase1,2 phase3 establish irc and pwr flash init device config self test setup drun lbist mbist flash init device config application execution t drb, min < t reset < t drb, max reset sequence start condition reset sequence trigger reset_b reset
docid023953 rev 4 101/126 spc56xl70lx electrical characteristics 125 figure 13. destructive reset sequence, bist disabled figure 14. external reset sequence long, bist enabled figure 15. functional reset sequence long phase3 phase1,2 phase0 establish irc and pwr flash init device config drun application execution t dr, min < t reset < t dr, max reset sequence trigger reset sequence start condition reset_b reset phase3 bist phase1,2 phase1,2 phase3 flash init device config self test setup drun lbist mbist flash init device config application execution t erlb, min < t reset < t erlb, max reset sequence trigger reset sequence start condition reset_b reset phase3 phase1,2 flash init device config drun application execution t frl, min < t reset < t frl, max reset sequence trigger reset sequence start condition reset_b reset
electrical characteristics spc56xl70lx 102/126 docid023953 rev 4 figure 16. functional reset sequence short the reset sequences shown in figure 15 and figure 16 are triggered by functional reset events. reset is driven low during these two reset sequences only if the corresponding functional reset source (which triggered the reset sequence) was enabled to drive reset low for the duration of the internal reset sequence (c) . 3.18.3 reset sequence trigger mapping the following table shows the possible trigger events for the different reset sequences. it specifies the reset sequence start conditions as well as the reset sequence end indications that are the basis for the timing data provided in tab le 3 0 . phase3 drun application execution t frs, min < t reset < t frs, max reset sequence trigger reset sequence start condition reset_b reset c. see rgm_fbre register for more details. table 31. reset sequence trigger ? reset sequence reset sequence trigger reset sequence start condition reset sequence end indication reset sequence destructive reset sequence, bist enabled (1) destructive reset sequence, bist disabled (1) external reset sequence long, bist enabled functional reset sequence long functional reset sequence short all internal destructive reset sources (lvds or internal hvd during power-up and during operation) section : destructive reset release of reset (2) triggers cannot trigger cannot trigger cannot trigger assertion of reset (3) section : external reset via reset cannot trigger triggers (4) triggers (5) triggers (6)
docid023953 rev 4 103/126 spc56xl70lx electrical characteristics 125 3.18.4 reset sequence ? start condition the impact of the voltage thresholds on the starting point of the internal reset sequence are becoming important if the voltage rails / signals ramp up with a very slow slew rate compared to the overall reset sequence duration. destructive reset figure 17 shows the voltage threshold that determines the start of the destructive reset sequence, bist enabled and the start for the destructive reset sequence, bist disabled . all internal functional reset sources configured for long reset sequence starts with internal reset trigger release of reset (7) cannot trigger cannot trigger triggers cannot trigger all internal functional reset sources configured for short reset cannot trigger cannot trigger cannot trigger triggers 1. whether bist is executed or not depends on the chip c onfiguration data stored in the shadow sector of the nvm. 2. end of the internal reset sequence (as specified in table 30 ) can only be observed by release of reset if it is not held low externally beyond the end of the inte rnal sequence which would prolong the internal reset phase3 till reset is released externally. 3. the assertion of reset can only trigger a reset sequence if the device was running (reset released) before. reset does not gate a destructive reset sequence, bist enabled or a destructive reset sequence, bist disabled . however, it can prolong these sequences if reset is held low externally beyond the end of the internal sequence (beyond phase3). 4. if reset is configured for long reset (default) and if bist is enabl ed via chip configuration data stored in the shadow sector of the nvm. 5. if reset is configured for long reset (default) and if bist is di sabled via chip configuration data stored in the shadow sector of the nvm. 6. if reset is configured for short reset 7. internal reset sequence can only be observed by state of reset if bidirectional reset functionality is enabled for the functional reset source which triggered the reset sequence. table 31. reset sequence trigger ? reset sequence (continued) reset sequence trigger reset sequence start condition reset sequence end indication reset sequence destructive reset sequence, bist enabled (1) destructive reset sequence, bist disabled (1) external reset sequence long, bist enabled functional reset sequence long functional reset sequence short
electrical characteristics spc56xl70lx 104/126 docid023953 rev 4 figure 17. reset sequence start for destructive resets external reset via reset figure 18 shows the voltage thresholds that determine the start of the reset sequences initiated by the assertion of reset as specified in tab le 31 . figure 18. reset sequence start via reset assertion t reset, max starts here t reset, min starts here supply rail v max t v v min table 32. voltage thresholds variable name value v min refer to table 17 v max refer to table 17 supply rail vdd_hv_pmu t reset, max starts here t reset, min starts here reset_b 0.65 * vdd_hv_io t v 0.35 * vdd_hv_io reset
docid023953 rev 4 105/126 spc56xl70lx electrical characteristics 125 3.18.5 external watchdog window if the application design requires the use of an external watchdog the data provided in section 3.18: reset sequence can be used to determine the correct positioning of the trigger window for the external watchdog. figure 19 shows the relationships between the minimum and the maximum duration of a given reset sequence and the position of an external watchdog trigger window. figure 19. reset sequence - external watchdog trigger window position 3.19 ac timing characteristics ac test timing conditions: unless otherwise noted, all test conditions are as follows: ? tj = ?40 o c to 150 o c ? supply voltages as specified in table 9 ? input conditions: all inputs: tr, tf = 1 ns ? output loading: all outputs: 50 pf 3.19.1 reset pin characteristics the spc56xl70 implements a dedicated bidirectional reset pin. external watchdog window closed earliest application start latest application start internal reset sequence start condition (signal or voltage rail) external watchdog window open t reset, min t reset, max t wdstart, min t wdstart, max external watchdog window closed external watchdog window open basic application init basic application init application time required to prepare watchdog trigger watchdog needs to be triggered within this window watchdog trigger application running application running
electrical characteristics spc56xl70lx 106/126 docid023953 rev 4 figure 20. start-up reset requirements figure 21. noise filtering on reset signal v il v dd device reset forced by reset v ddmin reset v ih device start-up phase v reset v il v ih v dd filtered by hysteresis filtered by lowpass filter w frst w nfrst hw_rst ?1? ?0? filtered by lowpass filter w frst unknown reset state device under hardware reset table 33. reset electrical characteristics no. symbol parameter conditions (1) min typ max unit 1t tr d output transition time output pin (2) c l = 25pf ? ? 12 ns c l = 50pf ? ? 25 c l = 100pf ? ? 40 2w frst p nreset input filtered pulse ? ? ? 40 ns 3w nfrst p nreset input not filtered pulse ? 500 ? ? ns 1. v dd = 3.3 v 10%, t j = ?40 c to +150 c, unless otherwise specified 2. c l includes device and package capacitance (c pkg <5pf)
docid023953 rev 4 107/126 spc56xl70lx electrical characteristics 125 3.19.2 wkup/nmi timing 3.19.3 ieee 1149.1 jtag interface timing figure 22. jtag test clock input timing table 34. wkup/nmi glitch filter no. symbol parameter min typ max unit 1w fnmi d nmi pulse width that is rejected ? ? 45 ns 2w nfnmi d nmi pulse width that is passed 205 ? ? ns table 35. jtag pin ac electrical characteristics no. symbol parameter conditions min max unit 1t jcyc d tck cycle time ? 62.5 ? ns 2t jdc d tck clock pulse width (measured at v dde /2) ? 40 60 % 3t tckrise d tck rise and fall times (40%?70%) ? ? 3 ns 4t tmss, t tdis d tms, tdi data setup time ? 5 ? ns 5t tmsh, t tdih d tms, tdi data hold time ? 25 ? ns 6t tdov d tck low to tdo data valid ? ? 20 ns 7t tdoi d tck low to tdo data invalid ? 0 ? ns 8t tdohz d tck low to tdo high impedance ? ? 20 ns 11 t bsdv d tck falling edge to output valid ? ? 50 ns 12 t bsdvz d tck falling edge to output valid out of high impedance ? ? 50 ns 13 t bsdhz d tck falling edge to output high impedance ? ? 50 ns 14 t bsdst d boundary scan input valid to tck rising edge ? 50 ? ns 15 t bsdht d tck rising edge to boundary scan input invalid ? 50 ? ns tck 1 2 2 3 3
electrical characteristics spc56xl70lx 108/126 docid023953 rev 4 figure 23. jtag test access port timing tck 4 5 6 7 8 tms, tdi tdo
docid023953 rev 4 109/126 spc56xl70lx electrical characteristics 125 figure 24. jtag boundary scan timing 3.19.4 nexus timing tck output signals input signals output signals 11 12 13 14 15 table 36. nexus debug port timing (1) no. symbol parameter conditions min max unit 1t mcyc d mcko cycle time ? 15.6 ? ns 2t mdc d mcko duty cycle ? 40 60 % 3t mdov d mcko low to mdo, mseo , evto data valid (2) ??0.10.25t mcyc 4t evtipw d evti pulse width ? 4.0 ? t tcyc 5t evtopw d evto pulse width ? 1 t mcyc 6t tcyc d tck cycle time (3) ?62.5?ns 7t tdc d tck duty cycle ? 40 60 % 8t ntdis, t ntmss d tdi, tms data setup time ? 8 ? ns 9t ntdih, t ntmsh d tdi, tms data hold time ? 5 ? ns 10 t jov d tck low to tdo data valid ? 0 25 ns 1. jtag specifications in this table apply when used for debug f unctionality. all nexus timing relative to mcko is measured from 50% of mcko and 50% of the respective signal. 2. for all nexus modes except ddr mode, mdo, mseo , and evto data is held valid until next mcko low cycle.
electrical characteristics spc56xl70lx 110/126 docid023953 rev 4 figure 25. nexus output timing figure 26. nexus ddr mode output timing 3. the system clock frequency needs to be four times faster than the tck frequency. 1 2 mcko mdo mseo evto output data valid 3 evti 4 5 mcko mdo, mseo mdo/mseo data are valid during mcko rising and falling edge
docid023953 rev 4 111/126 spc56xl70lx electrical characteristics 125 figure 27. nexus tdi, tms, tdo timing 3.19.5 external interrupt timing (irq pin) tdo 8 9 tms, tdi 10 tck 6 7 table 37. external interrupt timing no. symbol parameter conditions min max unit 1t ipwl d irq pulse width low ? 3 ? t cyc 2t ipwh d irq pulse width high ? 3 ? t cyc 3t icyc d irq edge to edge time (1) ?6?t cyc 1. applies when irq pins are configured for rising edge or falling edge events, but not both.
electrical characteristics spc56xl70lx 112/126 docid023953 rev 4 figure 28. external interrupt timing irq 1 2 3
docid023953 rev 4 113/126 spc56xl70lx electrical characteristics 125 3.19.6 dspi timing table 38. dspi timing no. symbol parameter conditions min max unit 1t sck d dspi cycle time master (mtfe = 0) 62 ? ns dslave (mtfe=0) 62 ? d slave receive only mode (1) 1. slave receive only mode can operate at a maximum frequency of 60 mhz. in this mode, the dspi can receive data on sin, but no valid data is transmitted on sout. 16 ? 2t csc d pcs to sck delay ? 16 ? ns 3t asc d after sck delay ? 16 ? ns 4t sdc d sck duty cycle ? t sck /2 - 10 t sck /2 + 10 ns 5t a d slave access time ss active to sout valid ? 40 ns 6t dis d slave sout disable time ss inactive to sout high-z or invalid ? 10 ns 7t pcsc d pcsx to pcss time ? 13 ? ns 8t pasc dpcss to pcsx time ? 13 ? ns 9t sui d data setup time for inputs master (mtfe = 0) 20 ? ns slave 2? master (mtfe = 1, cpha = 0) 5? master (mtfe = 1, cpha = 1) 20 ? 10 t hi d data hold time for inputs master (mtfe = 0) ?5 ? ns slave 4 ? master (mtfe = 1, cpha = 0) 11 ? master (mtfe = 1, cpha = 1) ?5 ? 11 t suo d data valid (after sck edge) master (mtfe = 0) ? 4 ns slave ? 23 master (mtfe = 1, cpha = 0) ? 12 master (mtfe = 1, cpha = 1) ? 4 12 t ho d data hold time for outputs master (mtfe = 0) ?2 ? ns slave 6 ? master (mtfe = 1, cpha = 0) 6 ? master (mtfe = 1, cpha = 1) ?2 ?
electrical characteristics spc56xl70lx 114/126 docid023953 rev 4 figure 29. dspi classic spi timing ? master, cpha = 0 figure 30. dspi classic spi timing ? master, cpha = 1 data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol=0) (cpol=1) 3 2 note: the numbers shown are referenced in table 38 . data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol=0) (cpol=1) note: the numbers shown are referenced in table 38 .
docid023953 rev 4 115/126 spc56xl70lx electrical characteristics 125 figure 31. dspi classic spi timing ? slave, cpha = 0 figure 32. dspi classic spi timing ? slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol=0) (cpol=1) note: the numbers shown are referenced in table 38 . 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) note: the numbers shown are referenced in table 38 .
electrical characteristics spc56xl70lx 116/126 docid023953 rev 4 figure 33. dspi modified transfer format timing ? master, cpha = 0 figure 34. dspi modified transfer format timing ? master, cpha = 1 pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol=0) (cpol=1) note: the numbers shown are referenced in table 38 . pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol=0) (cpol=1) note: the numbers shown are referenced in table 38 .
docid023953 rev 4 117/126 spc56xl70lx electrical characteristics 125 figure 35. dspi modified transfer format timing ? slave, cpha = 0 figure 36. dspi modified transfer format timing ? slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol=0) (cpol=1) 12 note: the numbers shown are referenced in table 38 . 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) note: the numbers shown are referenced in table 38 .
electrical characteristics spc56xl70lx 118/126 docid023953 rev 4 figure 37. dspi pcs strobe (pcss ) timing pcsx 7 8 pcss note: the numbers shown are referenced in table 38 .
docid023953 rev 4 119/126 spc56xl70lx package characteristics 125 4 package characteristics 4.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 4.2 package mechanical data figure 38. lqfp100 package mechanical drawing
package characteristics spc56xl70lx 120/126 docid023953 rev 4 table 39. lqfp100 mechanical data symbol mm inches (1) min typ max min typ max a ? ? 1.600 ? ? 0.0630 a1 0.050 ? 0.150 0.0020 ? 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 ? 0.200 0.0035 ? 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 ? 12.000 ? ? 0.4724 ? e 15.800 16.000 16.200 0.6220 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 ? 12.000 ? ? 0.4724 ? e ? 0.500 ? ? 0.0197 ? l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 ? 1.000 ? ? 0.0394 ? k 0.0 3.5 7.0 0.0 3.5 7.0 tolerance mm inches ccc 0.080 0.0031 1. values in inches are converted fr om mm and rounded to 4 decimal digits.
docid023953 rev 4 121/126 spc56xl70lx package characteristics 125 figure 39. lqfp144 package mechanical drawing table 40. lqfp144 mechanical data symbol mm inches (1) typ min max typ min max a ? ? 1.6 ? ? 0.0630 a1 ? 0.05 0.15 ? 0.0020 0.0059 a2 1.4 1.35 1.45 0.0551 0.0531 0.0571 b 0.22 0.17 0.27 0.0087 0.0067 0.0106 c ? 0.09 0.2 ? 0.0035 0.0079 d 22 21.8 22.2 0.8661 0.8583 0.8740 d1 20 19.8 20.2 0.7874 0.7795 0.7953 d3 17.5 ? ? 0.6890 ? ? e 22 21.8 22.2 0.8661 0.8583 0.8740 e1 20 19.8 20.2 0.7874 0.7795 0.7953
package characteristics spc56xl70lx 122/126 docid023953 rev 4 e3 17.5 ? ? 0.6890 ? ? e 0.5 ? ? 0.0197 ? ? l 0.6 0.45 0.75 0.0236 0.0177 0.0295 l1 1 ? ? 0.0394 ? ? k 3.5 0.0 7.0 3.5 0.0 7.0 tolerance mm inches ccc 0.08 0.0031 1. values in inches are converted from mm and rounded to four decimal digits. table 40. lqfp144 mechanical data (continued) symbol mm inches (1) typ min max typ min max
docid023953 rev 4 123/126 spc56xl70lx ordering information 125 5 ordering information figure 40. commercial product code structure (d) d. not all configurations are available in the market. pleas e contact your st sales representative, to get the list of orderable commercial part number. memory conditioning core family temperature package device spc56 70 el c l5 b example code: product identifier fy options y = tray r = tape and reel o = no flexray c = 80 mhz b = 120 mhz b = -40 o c to 105 o c c = -40 o c to 125 o c l3 = lqfp100 l5 = lqfp144 70 = 2 mb flash memory l = spc56xl family e = e200z4d dual core 4 = single core spc56 = power architecture in 90 nm 64 = 1.5 mb flash memory f= flexray s s = asild/sil3
revision history spc56xl70lx 124/126 docid023953 rev 4 6 revision history table 41. revision history date revision changes 23-nov-2012 1 initial release. 03-sep-2013 2 revision 2 changes: ? replaced iec with iso26262 in section 1.1: document overview ? updated section 3.14.1: input impedance and adc accuracy - replaced fc by fs ? table 6: system pins - added footnote to reset pin about weak pull down ? updated equation 11 ? updated table 25: flash memory program and erase electrical specifications - removed ?factory average? column and updated the values in ?initial max? column from rows 3 to 7 ? updated figure 40: commercial product code structure and added a note to the figure ? updated the following in table 8: absolute maximum ratings : updated the ?max? column values updated the table footnotes ? updated the following in table 9: recommended operating conditions (3.3 v) : added table footnote ?vdd_hv_adrx must always be applied and should be stable before lbist starts. if this supply is not above its absolute minimum level, lbist operations can fail? maximum values of v dd_hv_reg , v dd_hv_iox , v dd_hv_fla , v dd_hv_osc , v dd_hv_adv changed from ?3.6? to ?3.63? min and max value of v dd_hv_adr0 and v dd_hv_adr1 changed from ?4.5 to 5.5 or 3.0 to 3.6? to ?4.5 to 5.5 or 3.0 to 3.63? ? updated the following values in table 17: voltage regulator electrical specifications : for ?combined esr of external capacitor? min value is updated to ?1? and max value is updated to ?100? for ?main high voltage power - low voltage detection, upper threshold? max value is updated as ?2.93? added row ?digital supply low voltage detector lower threshold? for condition ?after a destructive reset initialization phase completion? added row ?digital supply low voltage detector upper threshold? for condition ?before a destructive reset initialization phase? for row ?digital supply high voltage detector upper threshold?, condition ?after a destructive reset initialization phase completion? min value is changed from ?1.38? to ?1.39?
docid023953 rev 4 125/126 spc56xl70lx revision history 125 03-sep-2013 2 (continued) ? updated the following in table 18: dc electrical characteristics : added table footnote ?the max input voltage on the adc pins is the adc reference voltage vdd_hv_adrx? updated v ol_f conditions from ?i ol = 1.5 ma? to ?i ol = 11 ma? updated v oh_f conditions from ?i oh = ? 1.5 ma? to ?i oh = ?11 ma? updated i inj parameter from ?dc injection current per pin? to ?dc injection current per pin (all bi-directional ports)? for i il row, parameter ?input leakage current(all adc input-only ports)? updated min value to ??0.25? and max value to ?0.25? ?for i il row, parameter ?input leakage current (shared adc input- only ports)? updated min value to ??0.3? and max value to ?0.3? ? updated the following in table 19: current consumption characteristics : specified oscillator bypass mode and crystal oscillator mode updated stop and halt mode values added idd_hv_pmu updated footnote 3 ? updated table 23: rc oscillator electrical characteristics ? updated the following in table 24: adc conversion characteristics : changed t conv to t eval and minimum value is changed from ?625? to ?600? table footnote 5 updated to ?this parameter does not include the sample time t sample , but only the time for determining the digital result? 17-sep-2013 3 updated disclaimer. 15-oct-2013 4 updated table 1 . table 41. revision history (continued) date revision changes
spc56xl70lx 126/126 docid023953 rev 4 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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